公开(公告)号：US20110284279A1

公开(公告)日：2011-11-24

申请号：US12790883

申请日：2010-05-31

Applicant: YING-TSO LAI ,  YUNG-CHIEH CHEN ,  CHUN-JEN CHEN ,  WEI-CHIEH CHOU

Inventor： YING-TSO LAI ,  YUNG-CHIEH CHEN ,  CHUN-JEN CHEN ,  WEI-CHIEH CHOU

IPC: H05K1/11

CPC classification number: H05K1/0225 ,  H05K1/0245 ,  H05K1/0253

Abstract: A printed circuit board includes a signal layer, a dielectric layer, and a reference layer. The signal layer includes a pair of differential signal lines. The dielectric layer is sandwiched between the signal layer and the reference layer. A first void is defined in the reference layer between projections of the pair of differential signal lines. Two second voids are defined in the reference layer at opposite sides of the projections of the pair of differential signal lines.

Abstract translation: 印刷电路板包括信号层，电介质层和参考层。 信号层包括一对差分信号线。 电介质层夹在信号层和参考层之间。 在该对差分信号线的投影之间的参考层中限定第一空隙。 在该对差分信号线的突起的相对侧的参考层中限定两个第二空隙。

公开(公告)号：US20110186337A1

公开(公告)日：2011-08-04

申请号：US12730238

申请日：2010-03-24

Applicant: WEI-CHIEH CHOU ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  TSUNG-SHENG HUANG

Inventor： WEI-CHIEH CHOU ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  TSUNG-SHENG HUANG

IPC: H05K1/09

CPC classification number: H05K1/09

Abstract: A printed circuit board (PCB) can prevent electrostatic discharge. A number of vias are embedded in the PCB. A circular insulated member is disposed between each via and the number of vias. Each via includes a layer of metal coated on an inner wall of a corresponding insulated member and a through hole bounded by the corresponding insulated member. An acute angle between two tangents which pass through a point of intersection of two overlapped insulated members is greater than twenty degrees.

Abstract translation: 印刷电路板（PCB）可以防止静电放电。 多个通孔嵌入在PCB中。 在每个通孔和多个通孔之间设置圆形绝缘构件。 每个通孔包括涂覆在相应的绝缘构件的内壁上的金属层和由对应的绝缘构件限定的通孔。 通过两个重叠绝缘部件的交点的两个切线之间的锐角大于二十度。

公开(公告)号：US20100321910A1

公开(公告)日：2010-12-23

申请号：US12497709

申请日：2009-07-06

Applicant: SHOU-KUO HSU ,  CHUN-JEN CHEN

Inventor： SHOU-KUO HSU ,  CHUN-JEN CHEN

IPC: H05K7/00

CPC classification number: H05K1/0231 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/0969 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A printed circuit board includes a first signal layer, a first reference layer, a second reference layer, and a second signal layer. An integrated circuit mounted on the first signal layer includes a power supply terminal connected to a first power supply via. The second signal layer includes a filter and a power supply wire. The filter includes a power terminal connected to the first power supply via, and a ground terminal connected to the second reference layer. The first power supply via is connected to the first reference layer through the power supply wire and a second power supply via. A void defined in the second reference layer is at least partially vertically overlapping with the power supply wire, and enables the first reference layer to function as a reference plane for the power supply wire, to increase impedance of the power supply wire.

Abstract translation: 印刷电路板包括第一信号层，第一参考层，第二参考层和第二信号层。 安装在第一信号层上的集成电路包括连接到第一电源通孔的电源端子。 第二信号层包括滤波器和电源线。 滤波器包括连接到第一电源通孔的电源端子和连接到第二参考层的接地端子。 第一电源通孔通过电源线和第二电源通孔连接到第一参考层。 限定在第二参考层中的空隙至少部分地与电源线垂直重叠，并且使得第一参考层能够用作电源线的参考平面，以增加电源线的阻抗。

公开(公告)号：US20090242244A1

公开(公告)日：2009-10-01

申请号：US12126748

申请日：2008-05-23

Applicant: SHOU-KUO HSU ,  CHUN-JEN CHEN

Inventor： SHOU-KUO HSU ,  CHUN-JEN CHEN

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09336

Abstract: An exemplary PCB includes a first reference layer, a first signal layer, and a second signal layer in that order. A first differential pair is arranged in the first signal layer in an edge-coupled structure referencing the first reference layer. A second differential pair is arranged in the second signal layer in edge-coupled structure. A first ground part and a second ground part are symmetrically arranged at opposite sides of the second differential pair in the second signal layer. The first differential pair is arranged above the first ground part and a projection of the first differential pair onto the second signal layer having an area coincident with the first ground part. The second differential pair references the first and second ground parts.

Abstract translation: 示例性的PCB包括第一参考层，第一信号层和第二信号层。 第一差分对以参考第一参考层的边缘耦合结构布置在第一信号层中。 第二差分对以边缘耦合结构布置在第二信号层中。 第一接地部分和第二接地部分对称地布置在第二信号层中的第二差分对的相对侧。 第一差分对布置在第一接地部分的上方，并且第一差分对的突起与具有与第一接地部分重合的区域的第二信号层上。 第二差分对参考第一和第二接地部分。

公开(公告)号：US20130007690A1

公开(公告)日：2013-01-03

申请号：US13441849

申请日：2012-04-07

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU ,  SHIN-TING YEN

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU ,  SHIN-TING YEN

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/78

Abstract: An electronic device reads a layout file of a printed circuit board (PCB) to be manufactured from a storage device, obtains length information and section area information of copper cladding distributed on power source areas and ground trace areas in each of one or more layers of the PCB to be manufactured by analyzing the layout file, and calculates power loss in each of the one or more layers according to the length information, the section area information, a resistance value of the copper cladding, and preset parameters of a power supply module and an integrated circuit (IC) load to be located on the PCB. In response to a determination that the power loss in the layer exceeds a preset range, the electronic device indicates the locations of the power source areas and the ground trace areas of a layer in the PCB layout file which need to be redesigned.

Abstract translation: 电子设备读取要从存储装置制造的印刷电路板（PCB）的布局文件，获得在一个或多个层中的每一个中的电源区域和地面迹线区域上分布的铜包层的长度信息和截面面积信息 通过分析布局文件来制造PCB，并且根据长度信息，截面面积信息，铜包层的电阻值和电源模块的预设参数来计算一个或多个层中的每一个中的功率损耗 以及位于PCB上的集成电路（IC）负载。 响应于层中的功率损耗超过预设范围的确定，电子设备指示需要重新设计的PCB布局文件中的层的电源区域和地面迹线区域的位置。

公开(公告)号：US20120292090A1

公开(公告)日：2012-11-22

申请号：US13166790

申请日：2011-06-22

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

IPC: H05K1/11

CPC classification number: H05K1/0265 ,  H05K1/11 ,  H05K2201/09663 ,  H05K2201/09845

Abstract: A printed circuit board (PCB) comprising a first circuit area, a second circuit area, a plurality of connecting elements, and a plurality of connecting terminals placed on the first circuit area, wherein the first circuit area are electrically connected to the second circuit area through the plurality of connecting elements, the plurality of connecting elements are arranged in sequence to extend toward the plurality of connecting terminals, to form shortest current paths from the second circuit area via corresponding one of the connecting elements to the connecting terminals, respectively, and each shortest current path between the corresponding one of the connecting elements and the corresponding one of the connecting terminals is uncoated with conductive material.

Abstract translation: 一种印刷电路板（PCB），包括第一电路区域，第二电路区域，多个连接元件和放置在第一电路区域上的多个连接端子，其中第一电路区域电连接到第二电路区域 通过多个连接元件，多个连接元件依次布置成朝向多个连接端子延伸，以形成从第二电路区域经由对应的一个连接元件到连接端子的最短电流路径，以及 连接元件与对应的一个连接端子之间的每个最短电流路径都不用导电材料涂覆。

公开(公告)号：US20120090884A1

公开(公告)日：2012-04-19

申请号：US12981460

申请日：2010-12-29

Applicant: TSUNG-SHENG HUANG ,  YING-TSO LAI ,  CHUN-JEN CHEN ,  WEI-CHIEH CHOU

Inventor： TSUNG-SHENG HUANG ,  YING-TSO LAI ,  CHUN-JEN CHEN ,  WEI-CHIEH CHOU

IPC: H05K1/11

CPC classification number: H05K1/0265 ,  H05K1/0201 ,  H05K1/116 ,  H05K2201/09309

Abstract: A printed circuit board includes a plurality of power layers. Each power layer defining a number of vias arranged in a number of rows. The number of the power layers is N (N>3). The power layers are defined as a 1st, 2nd, . . . , Nth power layer. The vias of the 1st power layer are connected to other power layers by a step-shaped connection means.

Abstract translation: 印刷电路板包括多个功率层。 每个功率层定义了以多行布置的多个通孔。 功率层的数量为N（N> 3）。 功率层定义为1，2，...。 。 。 ，第N功率层。 第一功率层的通孔通过阶梯形连接装置连接到其它功率层。

公开(公告)号：US20110093831A1

公开(公告)日：2011-04-21

申请号：US12790857

申请日：2010-05-31

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU ,  HSIEN-CHUAN LIANG ,  SHOU-KUO HSU

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU ,  HSIEN-CHUAN LIANG ,  SHOU-KUO HSU

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A system and method that can analyze a temperature rise of a printed circuit board (PCB). The system and method receives attribute parameters of the PCB from an input device, and generates a temperature rise formula according to the received attribute parameters. Additionally, the system and method calculates a temperature rise of a local area surrounding each component on the PCB according to the temperature rise formula.

Abstract translation: 可以分析印刷电路板（PCB）的温度升高的系统和方法。 该系统和方法从输入装置接收PCB的属性参数，并根据接收的属性参数生成温升公式。 另外，该系统和方法根据温升公式计算PCB上每个部件周围的局部区域的温度上升。

公开(公告)号：US20110051793A1

公开(公告)日：2011-03-03

申请号：US12633895

申请日：2009-12-09

Applicant: PO-CHUAN HSIEH ,  CHUN-JEN CHEN ,  CHIEN-HUNG LIU ,  YU-CHANG PAI ,  SHOU-KUO HSU

Inventor： PO-CHUAN HSIEH ,  CHUN-JEN CHEN ,  CHIEN-HUNG LIU ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC: H04B17/00

CPC classification number: H04B17/0085 ,  H04B17/21 ,  H04B17/23 ,  H04B17/327 ,  H04L1/0668

Abstract: A performance evaluation system for a multiple-input multiple-output (MIMO) antenna system receives simulation parameters from an input device, and simulates a MIMO antenna system accordingly. A method, also provided, further evaluates performance of the simulated MIMO antenna system when a series of radio frequency (RF) signals are transmitted through the MIMO antenna system, and displays a performance analysis result of the MIMO antenna system on a display device for evaluation of the performance of the simulated MIMO antenna system.

Abstract translation: 用于多输入多输出（MIMO）天线系统的性能评估系统从输入设备接收模拟参数，并相应地模拟MIMO天线系统。 还提供了一种方法，当通过MIMO天线系统传输一系列射频（RF）信号时，进一步评估模拟MIMO天线系统的性能，并且在用于评估的显示装置上显示MIMO天线系统的性能分析结果 的模拟MIMO天线系统的性能。

公开(公告)号：US20090278633A1

公开(公告)日：2009-11-12

申请号：US12168541

申请日：2008-07-07

Applicant: CHUN-JEN CHEN ,  SHOU-KUO HSU

Inventor： CHUN-JEN CHEN ,  SHOU-KUO HSU

IPC: H04B3/14

CPC classification number: H04L27/01 ,  H05K1/025 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10189

Abstract: An equalizer includes a first resistor and a capacitor connected in parallel. The positive terminal of the capacitor is connected to a signal transmission line on a blah printed circuit board. The negative terminal of the capacitor is connected to ground through a second resistor. A connector including the equalizer and a printed circuit board including the connector are also provided.

Abstract translation: 均衡器包括并联连接的第一电阻器和电容器。 电容器的正极端子连接到blah印刷电路板上的信号传输线。 电容器的负极通过第二个电阻连接到地。 还提供了包括均衡器的连接器和包括连接器的印刷电路板。