公开(公告)号：US09589627B1

公开(公告)日：2017-03-07

申请号：US15169508

申请日：2016-05-31

Applicant: Cadence Design Systems, Inc.

Inventor： Thomas Evan Wilson ,  Eric Harris Naviasky

IPC: G11C7/00 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/409 ,  H03K19/003 ,  H03K17/14

CPC classification number: G11C11/4074 ,  G11C5/145 ,  G11C7/1057 ,  G11C11/4096 ,  H03K17/145 ,  H03K19/00315

Abstract: Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation capacitor. One embodiment is high speed level translation memory driver apparatus comprising a plurality of field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) logic gates to drive the FETs, and a voltage translation capacitor with a first terminal of the voltage translation capacitor connected to an output of a second CMOS logic gate and a second terminal of the voltage translation capacitor connected to a gate terminal of a first P-type FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.

Abstract translation: 实施例涉及使用电压转换电容器来设计和创建存储器驱动器电路的系统，方法和计算机可读介质。 一个实施例是包括多个场效应晶体管（FET），互补金属氧化物半导体（CMOS）逻辑门以驱动FET的高速电平转换存储器驱动器装置，以及连接有电压转换电容器的第一端的电压转换电容器 连接到第一P型FET的栅极端子的第二CMOS逻辑门极和电压转换电容器的第二端子的输出。 还描述了包括其他电路，相关方法和包括与生成电路设计文件相关联的指令的媒体的附加实施例。

公开(公告)号：US11876521B1

公开(公告)日：2024-01-16

申请号：US17729088

申请日：2022-04-26

Applicant: Cadence Design Systems, Inc.

Inventor： Hajee Mohammed Shuaeb Fazeel ,  Jitendra Kumar Yadav ,  Thomas Evan Wilson

IPC: H03K5/134 ,  H03L7/081 ,  H03K5/00

CPC classification number: H03K5/134 ,  H03L7/0818 ,  H03K2005/00195

Abstract: The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.

公开(公告)号：US10958484B1

公开(公告)日：2021-03-23

申请号：US16806022

申请日：2020-03-02

Applicant: Cadence Design Systems, Inc.

Inventor： Hajee Mohammed Shuaeb Fazeel ,  Raksha ,  Thomas Evan Wilson

IPC: H04L25/03

Abstract: In some examples, a time-based equalizer can be configured to receive an input signal from a channel. The input signal can be distorted by previously received input signals transmitted over the channel. The time-based equalizer can be configured to compensate for distortions in the input signal caused by at least one previously received input signal to provide an ISI compensated input signal. The time-based equalizer can be configured to compensate for the distortions by edge time shifting respective edges of the input signal in time over a time interval for detecting the input signal to new edge time locations based on a feedback signal and edge movement signals. The feedback signal can be generated based on at least one previously received input signal.

公开(公告)号：US10545889B1

公开(公告)日：2020-01-28

申请号：US16215603

申请日：2018-12-10

Applicant: Cadence Design Systems, Inc.

Inventor： H Md Shuaeb Fazeel ,  Nikhil Sawarkar ,  Aaron Willey ,  Thomas Evan Wilson

IPC: G11C11/4093 ,  G06F13/16 ,  G06F17/50 ,  H03F3/45

Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from receiver arrangements that are not in autozero mode using multiplexer circuitry. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

公开(公告)号：US10345845B1

公开(公告)日：2019-07-09

申请号：US15943499

申请日：2018-04-02

Applicant: Cadence Design Systems, Inc.

Inventor： Ling Chen ,  Fuyue Wang ,  Thomas Evan Wilson ,  Jianyun Zhang ,  Eric Harris Naviasky

IPC: G05F3/16 ,  H03M1/46 ,  H03F1/30 ,  H03M1/38

Abstract: Aspects of the present disclosure include systems, methods, devices, and circuits for fast settling of a bias node. Consistent with some embodiments, a bias circuit may include a successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop configured to perform a fast settling process for a heavily loaded bias node. The SAR-ADC based loop performs a SAR-ADC process that includes measuring a reference signal to determine a number of cells in a capacitor array that are involved in a charge sharing process while simultaneously completing the settling process for the bias node.

公开(公告)号：US10161974B1

公开(公告)日：2018-12-25

申请号：US15943487

申请日：2018-04-02

Applicant: Cadence Design Systems, Inc.

Inventor： Ling Chen ,  Fuyue Wang ,  Thomas Evan Wilson ,  Jianyun Zhang ,  Eric Harris Naviasky

IPC: G01R23/09 ,  G01R19/00 ,  H03M3/02 ,  H03K7/06

Abstract: Aspects of the present disclosure include a frequency-to-current (F2I) circuit and systems, methods, devices, and other circuits related thereto. The F2I circuit is implemented with a delta-modulator-based control loop to settle and maintain an operating point on a bias node. The control loop provides an integral of an output of a comparator, and the comparator compares it to a self-built voltage reference. Upon powering on the circuit, an integrator in the control loop starts to integrate the charge on both a bias voltage and an internal voltage to provide a settling process for the internal voltage to approximate the reference voltage and for the bias voltage to approximate a predetermined operating point of the bias node. After the circuit has settled, the comparator's output charge toggles and the internal voltage and bias voltage become sawtooth-like waveforms at the reference voltage and operating points, respectively.