公开(公告)号：US07102944B1

公开(公告)日：2006-09-05

申请号：US11056049

申请日：2005-02-11

申请人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/419

摘要： The invention may comprise circuit for programmable control of a discharge deactivation signal when interfacing local bitlines to a global bitline or other circuit. The invention may also comprise a method for programmable ground circuit control for control of a discharge signal deactivation when interfacing local bitlines to a global bitline via a bitline evaluation discharge device comprising: providing input logic states to inputs of a controller circuit; outputting an adjustable ground value from the controller circuit; and controlling the bitline evaluation discharge device with the adjustable ground value.

公开(公告)号：US20130155787A1

公开(公告)日：2013-06-20

申请号：US13326727

申请日：2011-12-15

申请人： James W. Dawson ,  Noam Jungmann ,  Elazar Kachir ,  Udi Nir ,  Donald W. Plass

发明人： James W. Dawson ,  Noam Jungmann ,  Elazar Kachir ,  Udi Nir ,  Donald W. Plass

IPC分类号： G11C5/14 ,  G05F3/02

CPC分类号： G11C5/147

摘要： A digital voltage boost circuit, optionally working in parallel with an analog voltage regulator, periodically injects a constant amount of current each cycle into the bit line of a high density memory array to eliminate the bias voltage reduction which would otherwise occur. This results in a much faster recovery time and reduces the semiconductor real estate required. A pulse generator in the boost circuit generates one or more current modulation signals which control corresponding current supply devices in a current source. The boost circuit drives a constant amount of current to the bias voltage node each memory cycle.

摘要翻译： 可选地与模拟电压调节器并联的数字升压电路周期性地将恒定量的电流每周期注入高密度存储器阵列的位线，以消除否则将发生的偏置电压降低。 这导致恢复时间快得多，并减少了所需的半导体房地产。 升压电路中的脉冲发生器产生一个或多个电流调制信号，其控制电流源中的相应的电流供应装置。 升压电路驱动每个存储周期对偏置电压节点的恒定电流量。

公开(公告)号：US20130114361A1

公开(公告)日：2013-05-09

申请号：US13288424

申请日：2011-11-03

申请人： John E. Barth, JR. ,  Donald W. Plass ,  Adis Vehabovic

发明人： John E. Barth, JR. ,  Donald W. Plass ,  Adis Vehabovic

IPC分类号： G11C7/06 ,  H03F3/16

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the pull-up transistor drain node is pre-charged high and the pull-down transistor drain node receives an input signal. The switch is tripped, thereby making the electrical connection only when the voltage at the pull-down transistor drain node is less than the switch's trip voltage. In this case, the sense node discharges to the same level as the input signal. Otherwise, the switch prevents the electrical connection and the sense node remains high. The trip voltage depends on a reference voltage, which can be variable, thereby allowing the sensitivity of the sense amplifier to be selectively adjusted. Also disclosed are associated methods.

摘要翻译： 公开了一种读出放大器和包含它的存储器电路。 放大器包括交叉耦合的反相器，每个具有串联的下拉晶体管和上拉晶体管。 一个逆变器具有控制晶体管的漏极节点之间的电连接的电压控制开关。 在读操作期间，上拉晶体管漏极节点被预充电为高电平，并且下拉晶体管漏极节点接收输入信号。 开关跳闸，从而仅在下拉式晶体管漏极节点处的电压小于开关跳闸电压时进行电气连接。 在这种情况下，感测节点放电到与输入信号相同的电平。 否则，交换机可防止电气连接，并且感测节点保持高电平。 跳闸电压取决于可以变化的参考电压，从而允许选择性地调节读出放大器的灵敏度。 还公开了相关联的方法。

公开(公告)号：US20100268880A1

公开(公告)日：2010-10-21

申请号：US12424348

申请日：2009-04-15

申请人： Ravi Kumar Arimilli ,  Donald W. Plass ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Donald W. Plass ,  William John Starke

IPC分类号： G06F12/08 ,  G06F1/12

CPC分类号： G06F12/0886 ,  G06F9/30047 ,  G06F9/345

摘要： Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system.

摘要翻译： 公开了一种用于操作缓存系统的方法，系统和计算机程序产品。 高速缓存系统可以包括多个高速缓存行，并且多条高速缓存行的第一高速缓存行可以包括多个高速缓存单元，以及耦合到多个高速缓存单元的总线。 在一个或多个实施例中，总线可以包括可操作以接收第一控制信号并且将总线分为第一和第二部分或基于第一控制信号将总线聚合成整体的开关。 当总线被分离时，多个高速缓存单元的第一高速缓存单元和第二高速缓存单元耦合到总线的相应的第一和第二部分。 可以通过总线的各个部分选择来自第一和第二高速缓存单元的数据，并通过高速缓存系统的端口输出。

公开(公告)号：US07606060B2

公开(公告)日：2009-10-20

申请号：US11832190

申请日：2007-08-01

申请人： Yuen H. Chan ,  William V. Huott ,  Donald W. Plass

发明人： Yuen H. Chan ,  William V. Huott ,  Donald W. Plass

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C8/14

摘要： An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

摘要翻译： 由单个字线访问的SRAM单元和用于读取和写入操作的单独的存取晶体管。 一对写位线传输器件分别提供用于写操作的交叉耦合上拉，下拉晶体管对的右侧和左侧的访问以及与字线晶体管串联的单个读取位线晶体管，当 选中，读取单元格的内容。

公开(公告)号：US20080263417A1

公开(公告)日：2008-10-23

申请号：US12164869

申请日：2008-06-30

申请人： Tom Y. Chang ,  William V. Huott ,  Thomas J. Knips ,  Donald W. Plass

发明人： Tom Y. Chang ,  William V. Huott ,  Thomas J. Knips ,  Donald W. Plass

IPC分类号： G11C29/04 ,  G06F11/22

CPC分类号： G11C29/24 ,  G11C11/41 ,  G11C29/44 ,  G11C2029/0401 ,  G11C2029/1208 ,  G11C2029/4402

摘要： Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.

摘要翻译： 使用包括简单数据历史表在内的自检内置阵列。 该表用于跟踪在处理器或逻辑半导体芯片的任何级别的组装测试期间观察到的故障位置，其中芯片包含具有用于故障消除的冗余元件的SRAM宏。

公开(公告)号：US07283417B2

公开(公告)日：2007-10-16

申请号：US11054059

申请日：2005-02-09

申请人： John D. Davis ,  Paul A. Bunce ,  Donald W. Plass ,  Kenneth J. Reyer

发明人： John D. Davis ,  Paul A. Bunce ,  Donald W. Plass ,  Kenneth J. Reyer

IPC分类号： G11C8/00

CPC分类号： G11C11/413 ,  G11C7/18

摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

摘要翻译： 为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。 写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。 选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。 至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。 在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

公开(公告)号：US07266737B2

公开(公告)日：2007-09-04

申请号：US11180416

申请日：2005-07-13

申请人： Paul A. Bunce ,  John D. Davis ,  Patrick J. Meaney ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Patrick J. Meaney ,  Donald W. Plass

IPC分类号： G11C29/00

CPC分类号： G11C29/48 ,  G01R31/318533 ,  G11C29/88 ,  G11C2029/3202

摘要： A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.

摘要翻译： 扫描能够用RAM和关联电路的无缺陷备用元件替换缺陷存储器元件和相关电路的半导体存储器电路，以便在修复RAM之前更换有缺陷的RAM元件。 耦合一组置位/复位锁存器以接收来自存储器元件的信号，以及多路复用器控制电路，其被耦合以从多路复用器接收移位信号和ram_inhibit信号以向多路复用器部件提供特定的输入信号。 当扫描操作开始时，活动时钟信号将设置/复位锁存器设置为ram_inhibit模式，并且阻止存储器元件影响存储器输出锁存器的状态，由此当存储器操作开始时，有源时钟信号将复位置位/复位 锁存到系统模式以使多路复用器将适当的信号从存储器元件传递到输出锁存器，并且备用存储器元件被激活以替换有缺陷的存储器元件。

公开(公告)号：US07219275B2

公开(公告)日：2007-05-15

申请号：US11053631

申请日：2005-02-08

申请人： Tom Y. Chang ,  William V. Huott ,  Thomas J. Knips ,  Donald W. Plass

发明人： Tom Y. Chang ,  William V. Huott ,  Thomas J. Knips ,  Donald W. Plass

IPC分类号： G11C29/00 ,  G01R31/28

CPC分类号： G11C29/802 ,  G11C11/41 ,  G11C29/44

摘要： A method and apparatus for providing flexible modular redundancy allocation for memory built in self test of random access memory with redundancy. The apparatus includes a first redundancy support register that includes inputs for receiving an address of a location in memory under test and data relating to must fix repair elements. The address includes a row and column vector of the location. The first redundancy support register also includes outputs for transmitting the address and data. The apparatus also includes a second redundancy support register including inputs for receiving the address and data from the outputs of the first redundancy support register. Each of the inputs of the second redundancy support register shares a one-to-one correspondence to each of the outputs of the first redundancy support register. The apparatus further includes allocation logic for providing a modular implementation of the first redundancy support register and the second redundancy support register.

摘要翻译： 一种为具有冗余的随机存取存储器的自检中构建的存储器提供灵活的模块冗余分配的方法和装置。 该装置包括第一冗余支持寄存器，其包括用于接收被测存储器中的位置的地址的输入，以及必须修复修复元件的数据。 该地址包括位置的行和列向量。 第一冗余支持寄存器还包括用于发送地址和数据的输出。 该装置还包括第二冗余支持寄存器，其包括用于从第一冗余支持寄存器的输出接收地址和数据的输入。 第二冗余支持寄存器的每个输入与第一冗余支持寄存器的每个输出共享一一对应关系。 该装置还包括用于提供第一冗余支持寄存器和第二冗余支持寄存器的模块化实现的分配逻辑。

公开(公告)号：US07176725B2

公开(公告)日：2007-02-13

申请号：US11050895

申请日：2005-02-04

申请人： James W. Dawson ,  Donald W. Plass ,  Kenneth J. Reyer

发明人： James W. Dawson ,  Donald W. Plass ,  Kenneth J. Reyer

IPC分类号： H03K19/094 ,  H03K19/096

CPC分类号： H03K19/0963

摘要： A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage.

摘要翻译： 解码器电路包括具有多个扇入输入的脉冲供电级，由脉冲供电级馈送的动态级，以及通过传递器件选择性地耦合到脉冲供电级的输出节点的复制节点。 通过装置和动态级由时钟信号控制，以便能够利用动态级的时钟启用来对脉冲级的自定时评估。