公开(公告)号：US07102153B2

公开(公告)日：2006-09-05

申请号：US10919323

申请日：2004-08-17

Applicant: Pang-Shiu Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

Inventor： Pang-Shiu Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

IPC: H01L29/06

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02532

Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

公开(公告)号：US06963089B2

公开(公告)日：2005-11-08

申请号：US10720117

申请日：2003-11-25

Applicant: Jin-Wei Shi ,  Chee-Wee Liu

Inventor： Jin-Wei Shi ,  Chee-Wee Liu

IPC: H01L31/08 ,  H01L31/107

CPC classification number: B82Y10/00 ,  H01L31/107

Abstract: An avalanche photo-detector (APD) is disclosed, which can reduce device capacitance, operating voltage, carrier transport time and dark current as well as increasing response speed and output power. Thus, an avalanche photo-detector (APD) with high saturation power, high gain-bandwidth product, low noise, fast response, low dark current is achieved. The APD includes an absorption layer with graded doping for converting an incident light into carriers, an undoped multiplication layer for multiplying current by means of receiving carriers, a doped field buffer layer sandwiched between the absorption layer and the multiplication layer for concentrating an electric field in the multiplication layer when a bias voltage is applied, and an undoped drift layer sandwiched between the absorption layer and the field buffer layer for capacitance reduction.

Abstract translation: 公开了一种雪崩光电检测器（APD），可以降低器件电容，工作电压，载流子传输时间和暗电流以及响应速度和输出功率。 因此，实现了具有高饱和功率，高增益带宽乘积，低噪声，快速响应，低暗电流的雪崩光电检测器（APD）。 APD包括具有用于将入射光转换成载流子的渐变掺杂的吸收层，用于通过接收载流子来乘以电流的未掺杂乘法层，夹在吸收层和乘法层之间的掺杂场缓冲层，用于将电场集中 施加偏置电压时的倍增层和夹在吸收层和场缓冲层之间的未掺杂漂移层用于电容降低。

公开(公告)号：US20050153491A1

公开(公告)日：2005-07-14

申请号：US10838252

申请日：2004-05-05

Applicant: Yang-Tai Tseng ,  Pang-Shiu Chen ,  Chee-Wee Liu

Inventor： Yang-Tai Tseng ,  Pang-Shiu Chen ,  Chee-Wee Liu

IPC: C30B1/02 ,  C30B29/52 ,  H01L21/20 ,  H01L21/265 ,  H01L29/10 ,  H01L21/00 ,  H01L21/84 ,  H01L21/76 ,  C30B1/00

CPC classification number: H01L21/26506 ,  C30B1/023 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02694 ,  H01L29/1054

Abstract: A process of forming a low-strain crystal layer having low cell dislocation, low surface roughness and low thickness comprises: forming at least one crystal layer on a substrate; patterning the crystal layer by exposure and development to form an ion-doping region; doping ions in the ion-doping region of the crystal layer to convert the crystal layer to an amorphous layer; performing a planarization process on the amorphous layer; and annealing the amorphous layer to convert the amorphous layer to a low-strain crystal layer.

Abstract translation: 形成具有低电池位错，低表面粗糙度和低厚度的低应变晶体层的工艺包括：在衬底上形成至少一个晶体层; 通过曝光和显影来图案化晶体层以形成离子掺杂区域; 在晶体层的离子掺杂区域掺杂离子以将晶体层转化为非晶层; 对非晶层进行平面化处理; 并且使非晶层退火以将非晶层转变成低应变晶体层。

公开(公告)号：US06916674B2

公开(公告)日：2005-07-12

申请号：US10704632

申请日：2003-11-12

Applicant: Pang-Shiu Chen ,  Buo-Chin Hsu ,  Chee-Wee Liu

Inventor： Pang-Shiu Chen ,  Buo-Chin Hsu ,  Chee-Wee Liu

IPC: H01L21/20 ,  H01L21/31 ,  H01L31/0352 ,  H01L33/00 ,  H01L21/00

CPC classification number: B82Y10/00 ,  B82Y20/00 ,  H01L21/02373 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0259 ,  H01L31/0352

Abstract: The present invention discloses a method for fabricating multiple-thickness insulator layers via strain field generated by stress. The strain field is used for alternating a develop mechanism of insulator layers on the quantum dots. By forming the multiple-thickness insulator layers at various developing rates, not only leakage current is prevented, but also components are kept isolated in the nano-electronics components. In nano-electronics manufacturing, the method for fabricating multiple-thickness insulator layers results in both better product reliability and the yield rate. It is potential for integral circuit manufacturing.

Abstract translation: 本发明公开了一种通过应力产生的应变场来制造多层绝缘体层的方法。 应变场用于交替量子点上的绝缘体层的显影机制。 通过以各种显影速率形成多层绝缘体层，不仅可以防止泄漏电流，还可以在纳米电子部件中保持隔离。 在纳米电子制造中，制造多层绝缘体层的方法产生更好的产品可靠性和产率。 它是集成电路制造的潜力。

公开(公告)号：US20050045870A1

公开(公告)日：2005-03-03

申请号：US10919323

申请日：2004-08-17

Applicant: Pang Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

Inventor： Pang Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

IPC: C30B1/00 ,  H01L21/20 ,  H01L21/36 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L33/00

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02532

Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

Abstract translation: 公开了一种用于在衬底上生长具有多个Ge量子点（QD）的应变Si层和松弛SiGe层的方法。 该方法可以减少穿透位错密度，降低应变硅的表面粗糙度，并进一步缩短形成外延层的生长时间，而不是常规方法。 该方法包括以下步骤：提供硅衬底，形成多个Ge量子点层; 形成一层轻松的SixGe1-x; 并在亚序列中形成应变硅层; 其中x大于0且小于1。

公开(公告)号：US20090194152A1

公开(公告)日：2009-08-06

申请号：US12025226

申请日：2008-02-04

Applicant: Chee-Wee Liu ,  Cheng-Yeh Yu ,  Wen-Yuan Chen ,  Chu-Hsuan Lin

Inventor： Chee-Wee Liu ,  Cheng-Yeh Yu ,  Wen-Yuan Chen ,  Chu-Hsuan Lin

IPC: H01L31/0336 ,  H01L31/18

CPC classification number: H01L31/022425 ,  B82Y20/00 ,  H01L31/022433 ,  H01L31/028 ,  H01L31/035254 ,  H01L31/035281 ,  H01L31/072 ,  H01L31/0745 ,  H01L31/075 ,  H01L31/1804 ,  H01L31/1812 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

Abstract: A thin-film solar cell having a hetero-junction of semiconductor and the fabrication method thereof are provided. Instead of the conventional hetero-junction of III-V semiconductor or homo-structure of IV semiconductor, the thin-film solar cell according to the present invention adopts a novel hetero-junction structure of IV semiconductor to improve the cell efficiency thereof. By adjusting the amount of layer sequences and the thickness of the hetero-junction structure, the cell efficiency of the thin-film solar cell according to the present invention is also optimized.

Abstract translation: 提供了具有半导体异质结的薄膜太阳能电池及其制造方法。 代替III-V族半导体的常规异质结或IV半导体的同构结构，根据本发明的薄膜太阳能电池采用IV半导体的新型异质结结构来提高其电池效率。 通过调整层序列的量和异质结结构的厚度，也优化了本发明的薄膜太阳能电池的电池效率。

公开(公告)号：US07498224B2

公开(公告)日：2009-03-03

申请号：US11489470

申请日：2006-07-20

Applicant: Pang-Shiu Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

Inventor： Pang-Shiu Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

IPC: H01L21/8242 ,  H01L21/66 ,  H01L21/336 ,  H01L21/8234

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02532

Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

Abstract translation: 公开了一种用于在衬底上生长具有多个Ge量子点（QD）的应变Si层和松弛SiGe层的方法。 该方法可以减少穿透位错密度，降低应变硅的表面粗糙度，并进一步缩短形成外延层的生长时间，而不是常规方法。 该方法包括以下步骤：提供硅衬底，形成多个Ge量子点层; 形成一层轻松的SixGe1-x; 并在亚序列中形成应变硅层; 其中x大于0且小于1。

公开(公告)号：US07282414B2

公开(公告)日：2007-10-16

申请号：US10909403

申请日：2004-08-03

Applicant: Min-Hung Lee ,  Cheng-Yeh Yu ,  Shing-Chii Lu ,  Chee-Wee Liu

Inventor： Min-Hung Lee ,  Cheng-Yeh Yu ,  Shing-Chii Lu ,  Chee-Wee Liu

IPC: H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/938

Abstract: Fabrication methods for compressive strained-silicon by ion implantation. Ions are implanted into a silicon-containing substrate and high temperature processing converts the vicinity of the ion-contained region into strained-silicon. Transistors fabricated by the method are also provided.

Abstract translation: 通过离子注入制备压应变硅的制备方法。 将离子注入到含硅衬底中，并且高温处理将离子包含区域的附近转变成应变硅。 还提供了通过该方法制造的晶体管。

公开(公告)号：US20060099772A1

公开(公告)日：2006-05-11

申请号：US10982375

申请日：2004-11-05

Applicant: Cheng-Ya Yu ,  Sun-Rong Jan ,  Shu-Tong Chang ,  Chee-Wee Liu

Inventor： Cheng-Ya Yu ,  Sun-Rong Jan ,  Shu-Tong Chang ,  Chee-Wee Liu

IPC: H01L21/46

CPC classification number: H01L21/7624 ,  H01L21/823807 ,  H01L29/7842 ,  H01L29/786

Abstract: A method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices is disclosed. The method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices includes the following steps: (a) providing a substrate, (b) fixing the substrate, (c) applying a stress upon the substrate, and (d) inducing a strain in one of a device and a circuit by stressing the substrate.

Abstract translation: 公开了一种具有用于增强集成电路或装置的速度的机械应变硅的方法。 具有用于增强集成电路或器件的速度的机械应变硅的方法包括以下步骤：（a）提供衬底，（b）固定衬底，（c）在衬底上施加应力，以及（d）诱导 通过施加基板在器件和电路之一中的应变。

公开(公告)号：US06759694B1

公开(公告)日：2004-07-06

申请号：US10718621

申请日：2003-11-24

Applicant: Yu-Min Hsu ,  Jin-Wei Shi ,  Zing-Way Pei ,  Fon Yuan ,  Chee-Wee Liu

Inventor： Yu-Min Hsu ,  Jin-Wei Shi ,  Zing-Way Pei ,  Fon Yuan ,  Chee-Wee Liu

IPC: H01L3111

CPC classification number: H01L31/1105 ,  H01L31/0352

Abstract: A phototransistor structure is disclosed. A sidewall is grown on the collector side and under the base. The surface of the sidewall is formed with a sidewall contact. When the contact is connected to an external voltage, the holes accumulated at the junction of the base and emitter can be quickly removed. This solves the problem in the prior art that using a bias between the base and the emitter to remove holes usually results in a large dark current (bias current), power consumption, and diminishing optoelectronic conversion gain.

Abstract translation: 公开了一种光电晶体管结构。 侧壁在集电器侧和底部下生长。 侧壁的表面形成有侧壁接触。 当触点连接到外部电压时，可以快速去除在基极和发射极的结点处积累的空穴。 这解决了现有技术中使用基极和发射极之间的偏置来去除空穴的问题通常导致大的暗电流（偏置电流），功耗和光电转换增益的减小。