公开(公告)号：US20120243363A1

公开(公告)日：2012-09-27

申请号：US13492469

申请日：2012-06-08

Applicant: Cheng Hung LEE

Inventor： Cheng Hung LEE

IPC: G11C5/14

CPC classification number: H01L27/0207 ,  H01L27/105

Abstract: An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block.

Abstract translation: 集成电路（IC）芯片包括具有包含至少两条电源线的第一金属层的第一存储单元阵列块和包含彼此独立的至少两条电源线的第二存储单元阵列块，其中所有电源线在 服务于第一存储单元阵列块的第一金属层不延伸到第二存储单元阵列块中，并且服务于第二存储单元阵列块的第一金属层上的所有电力线不延伸到第一存储单元阵列块中。

公开(公告)号：US20120106269A1

公开(公告)日：2012-05-03

申请号：US12913087

申请日：2010-10-27

Applicant: Cheng Hung LEE ,  Jung-Ping YANG

Inventor： Cheng Hung LEE ,  Jung-Ping YANG

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/067

Abstract: The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver.

Abstract translation: 本申请公开了一种具有配置成承载第一数据线信号的第一数据线和被配置为承载第二数据线信号的第二数据线的存储器电路。 此外，第一驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第二数据线信号建立用于第一数据线的第一电流路径。 类似地，第二驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第一数据线信号为第二数据线建立第二电流路径。 存储器电路还具有第一驱动器使能线，其被配置为选择性地使第一驱动器和第二驱动器使能线被配置为选择性地启用第二驱动器。

公开(公告)号：US20120195139A1

公开(公告)日：2012-08-02

申请号：US13443619

申请日：2012-04-10

Applicant: Hsu-Shun CHEN ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Chung-Yi WU ,  Chih-Chieh CHIU

Inventor： Hsu-Shun CHEN ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Chung-Yi WU ,  Chih-Chieh CHIU

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C7/1048 ,  G11C5/14

Abstract: In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

Abstract translation: 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

公开(公告)号：US20110090753A1

公开(公告)日：2011-04-21

申请号：US12885826

申请日：2010-09-20

Applicant: Cheng Hung LEE ,  Chung-Yi WU ,  Hsu-Shun CHEN ,  Chung-Ji LU

Inventor： Cheng Hung LEE ,  Chung-Yi WU ,  Hsu-Shun CHEN ,  Chung-Ji LU

IPC: G11C5/14

CPC classification number: G11C11/413

Abstract: An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In a deep sleep mode the supply voltage (e.g., VDDI) for the bit cell in the SRAM macro is lowered by about 20-40% of the SRAM supply voltage (e.g., VDD), sufficient to retain the data in the bit cell. When access to the SRAM is not needed, the SRAM operates in the sleep mode, consuming little or no power.

Abstract translation: SRAM包括被配置用于使用不同的电压电平在不同的操作模式下工作的电路，其中基于操作模式调节电压电平和因此的电流泄漏。 例如，在正常工作模式下，SRAM将作为其他SRAM消耗电力。 在深度睡眠模式下，SRAM宏中的位单元的电源电压（例如，VDDI）降低SRAM电源电压（例如VDD）的约20-40％，足以将数据保留在位单元中。 当不需要访问SRAM时，SRAM在睡眠模式下运行，消耗很少或没有电源。

公开(公告)号：US20130010516A1

公开(公告)日：2013-01-10

申请号：US13178021

申请日：2011-07-07

Applicant: Cheng Hung LEE ,  XiuLi YANG ,  Liangbo ZHUANG

Inventor： Cheng Hung LEE ,  XiuLi YANG ,  Liangbo ZHUANG

IPC: G11C5/06 ,  G06F17/50

CPC classification number: G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/005

Abstract: A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.

Abstract translation: 一种半导体存储器芯片，其具有由相应的字线驱动器和位线驱动的字线，以将信号传送到具有位线和位线存储器单元的交叉处的存储器单元的各个位线放大器/驱动器。 包括各种存储单元类型的半导体存储器芯片，基于字线和位线之间的交点的位置的交叉路口处的存储单元的类型。

公开(公告)号：US20120092939A1

公开(公告)日：2012-04-19

申请号：US12917708

申请日：2010-11-02

Applicant: Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chung-Ji LU ,  Cheng Hung LEE

Inventor： Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chung-Ji LU ,  Cheng Hung LEE

IPC: G11C7/12 ,  G11C7/06

CPC classification number: G11C7/067 ,  G11C7/12 ,  G11C11/419

Abstract: A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground.

Abstract translation: 具有单端感测方案的存储器包括位线，耦合到位线的存储单元和预充电电路。 预充电电路被配置为将位线预充电到电源电压和地之间的预充电电压。

公开(公告)号：US20120061764A1

公开(公告)日：2012-03-15

申请号：US12879447

申请日：2010-09-10

Applicant: Annie LUM ,  Derek C. TAO ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Vineet Kumar AGRAWAL ,  Keun-Young KIM ,  Pyong Yun CHO

Inventor： Annie LUM ,  Derek C. TAO ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Vineet Kumar AGRAWAL ,  Keun-Young KIM ,  Pyong Yun CHO

IPC: H01L27/088 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/088 ,  Y02P90/265

Abstract: The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.

Abstract translation: 上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。 这种扩散区域的扩展可解决或减少LOD和边缘效应问题。 此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。 虚拟设备被禁用，其性能不重要。 因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

公开(公告)号：US20120020179A1

公开(公告)日：2012-01-26

申请号：US12839490

申请日：2010-07-20

Applicant: You-Cheng XIAO ,  Hong-Chen CHENG ,  Chung-Ji LU ,  Cheng Hung LEE ,  Jung-Hsuan CHEN ,  Li-Chun TIEN

Inventor： You-Cheng XIAO ,  Hong-Chen CHENG ,  Chung-Ji LU ,  Cheng Hung LEE ,  Jung-Hsuan CHEN ,  Li-Chun TIEN

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C11/413

Abstract: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.

Abstract translation: 字线解码器包括多个驱动器电路，设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。 字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。 字线解码器还包括耦合到每个主输入线的本地解码线。 字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。 集群解码线耦合到解码线。 字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。

公开(公告)号：US20120106286A1

公开(公告)日：2012-05-03

申请号：US12912971

申请日：2010-10-27

Applicant: Cheng Hung LEE ,  Hsu-Shun CHEN

Inventor： Cheng Hung LEE ,  Hsu-Shun CHEN

IPC: G11C8/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/10 ,  G11C11/418

Abstract: The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals.

Abstract translation: 本申请公开了一种存储器电路，其具有耦合到第一存储体并被配置为接收多个地址控制信号并且响应于多个地址控制信号产生第一多个小区选择信号的第一解码器， 耦合到第二存储体并且被配置为接收多个反相地址控制信号，并响应于所述多个反相地址控制信号产生第二多个单元选择信号。 存储器电路还具有耦合到第二解码器的地址控制信号缓冲器，并且被配置为将多个地址控制信号转换成多个反相地址控制信号。

公开(公告)号：US20120147688A1

公开(公告)日：2012-06-14

申请号：US13397102

申请日：2012-02-15

Applicant: Yen-Huei CHEN ,  Cheng Hung LEE

Inventor： Yen-Huei CHEN ,  Cheng Hung LEE

IPC: G11C5/14

CPC classification number: G11C11/413 ,  G11C11/412

Abstract: An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage.

Abstract translation: 集成电路包括用于存储数据的至少一个存储器阵列。 第一开关与存储器阵列耦合。 第一电力线与第一开关耦合。 第一电力线可操作以提供第一电力电压。 第二开关与存储器阵列耦合。 第二电源线与第二开关耦合。 第二电源线可操作以在保持模式期间提供用于保留数据的第二电源电压。 第三电源线与存储器阵列耦合。 第三电源线能够提供第三电源电压。