ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES
    11.
    发明申请
    ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES 有权
    用于互连结构的增强扩展障碍

    公开(公告)号:US20120326311A1

    公开(公告)日:2012-12-27

    申请号:US13164929

    申请日:2011-06-21

    IPC分类号: H01L23/532 H01L21/768

    摘要: Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, the method includes forming at least one opening into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is formed on the nitrogen enriched dielectric surface. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner. The conductive material, the metal diffusion barrier liner and the metal nitride liner that are located outside of the at least one opening are removed to provide a planarized conductive material, a planarized metal diffusion barrier liner and a planarized metal nitride liner, each of which includes an upper surface that is co-planar with the nitrogen enriched dielectric surface layer of the interconnect dielectric material.

    摘要翻译: 提供制造互连结构的替代方法,其中提供包括在互连电介质材料和上覆金属扩散阻挡衬里之间形成的原位形成的金属氮化物衬垫的增强扩散屏障。 在一个实施例中,该方法包括在互连电介质材料中形成至少一个开口。 利用热氮化在互连电介质的暴露表面内形成富氮介电表面层。 在富氮电介质表面上形成金属扩散阻挡衬垫。 在形成金属扩散阻挡衬里期间和/或之后,金属氮化物衬垫在金属扩散阻挡衬里的下部区域中原位形成。 然后在金属扩散阻挡衬里上形成导电材料。 移除位于至少一个开口外侧的导电材料,金属扩散阻挡衬垫和金属氮化物衬垫,以提供平坦化的导电材料,平坦化的金属扩散阻挡衬垫和平坦化的金属氮化物衬垫,每个衬垫包括 与互连电介质材料的富氮介电表面层共平面的上表面。

    Large grain size conductive structure for narrow interconnect openings
    13.
    发明授权
    Large grain size conductive structure for narrow interconnect openings 有权
    用于窄互连开口的大粒度导电结构

    公开(公告)号:US07956463B2

    公开(公告)日:2011-06-07

    申请号:US12560878

    申请日:2009-09-16

    IPC分类号: H01L23/48

    摘要: An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer, a grain growth promotion layer, an agglomerated plating seed layer, an optional second plating seed layer a conductive structure. The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation.

    摘要翻译: 提供具有降低的电阻的互连结构和形成这种互连结构的方法。 互连结构包括其中包括至少一个开口的电介质材料。 至少一个开口填充有可选的阻挡扩散层,晶粒生长促进层,聚集的电镀种子层,任选的第二电镀种子层,导电结构。 包含含金属的导电材料(通常为Cu)的导电结构具有竹结构,平均晶粒尺寸大于0.05微米。 在一些实施例中,导电结构包括具有(111)晶体取向的导电晶粒。

    LARGE GRAIN SIZE CONDUCTIVE STRUCTURE FOR NARROW INTERCONNECT OPENINGS
    14.
    发明申请
    LARGE GRAIN SIZE CONDUCTIVE STRUCTURE FOR NARROW INTERCONNECT OPENINGS 有权
    用于窄幅互连开口的大粒度导电结构

    公开(公告)号:US20110062587A1

    公开(公告)日:2011-03-17

    申请号:US12560878

    申请日:2009-09-16

    IPC分类号: H01L23/522 H01L21/768

    摘要: An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer, a grain growth promotion layer, an agglomerated plating seed layer, an optional second plating seed layer a conductive structure. The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation.

    摘要翻译: 提供具有降低的电阻的互连结构和形成这种互连结构的方法。 互连结构包括其中包括至少一个开口的电介质材料。 至少一个开口填充有可选的阻挡扩散层,晶粒生长促进层,聚集的电镀种子层,任选的第二电镀种子层,导电结构。 包含含金属的导电材料(通常为Cu)的导电结构具有竹结构,平均晶粒尺寸大于0.05微米。 在一些实施例中,导电结构包括具有(111)晶体取向的导电晶粒。

    STRUCTURE FOR METAL CAP APPLICATIONS
    15.
    发明申请
    STRUCTURE FOR METAL CAP APPLICATIONS 有权
    金属盖应用结构

    公开(公告)号:US20110003473A1

    公开(公告)日:2011-01-06

    申请号:US12881806

    申请日:2010-09-14

    IPC分类号: H01L21/768

    摘要: An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.

    摘要翻译: 提供了一种互连结构,其中嵌入电介质材料内的导电特征被金属覆盖层封盖,但在最终结构中绝缘材料表面上没有金属残留物。 与现有技术的互连结构相比,本发明的互连结构具有改善的介电击穿强度。 此外,本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。 本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料,其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。 电介质覆盖层位于电介质材料上,并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

    HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD
    16.
    发明申请
    HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD 失效
    高比例电镀金属特征及方法

    公开(公告)号:US20090148677A1

    公开(公告)日:2009-06-11

    申请号:US11953359

    申请日:2007-12-10

    IPC分类号: C25D5/02 B32B3/00

    摘要: Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

    摘要翻译: 公开了改进的高宽比电镀金属结构(例如,铜或铜合金互连,例如线的后端(BEOL)或线的中间(MOL)接触)的实施例,其中电镀金属填充材料 没有接缝和/或空隙。 此外,公开了通过用金属电镀种子层衬里高纵横比开口(例如,高纵横比通孔或沟槽)形成这种电镀金属结构的方法的实施例,然后在其上形成保护层 金属电镀种子层的一部分与开口侧壁相邻,使得随后的电镀仅从开口的底表面发生。

    AIR GAP STRUCTURE HAVING PROTECTIVE METAL SILICIDE PADS ON A METAL FEATURE
    17.
    发明申请
    AIR GAP STRUCTURE HAVING PROTECTIVE METAL SILICIDE PADS ON A METAL FEATURE 有权
    在金属特征上具有保护性金属硅化物垫的气隙结构

    公开(公告)号:US20090140428A1

    公开(公告)日:2009-06-04

    申请号:US11949189

    申请日:2007-12-03

    IPC分类号: H01L23/52 H01L21/4763

    摘要: A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

    摘要翻译: 在包括低k材料层和嵌入其中的金属特征的互连结构上形成硬掩模。 将嵌段聚合物施加到硬掩模层上,自组装和图案化以形成聚合物嵌段组分的聚合物基质并且包含圆柱形孔。 蚀刻硬掩模和低k材料层以形成空腔。 导电材料镀在暴露的金属表面上,包括金属特征的顶表面的部分以形成金属垫。 金属硅化物焊盘通过将金属焊盘暴露于含硅气体而形成。 进行蚀刻以放大和合并低k材料层中的空腔。 通过金属硅化物焊盘防止金属特征被蚀刻。 形成具有空隙并且没有金属特征表面的缺陷的互连结构。

    SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS
    18.
    发明申请
    SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS 失效
    用于保险丝和抗 - 保险丝应用的半导体结构

    公开(公告)号:US20080296728A1

    公开(公告)日:2008-12-04

    申请号:US11755995

    申请日:2007-05-31

    IPC分类号: H01L23/525 H01L21/768

    摘要: A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.

    摘要翻译: 提供了一种保险丝/反熔丝结构,其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。 小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层,并且熔丝元件内的导电材料扩散到相邻的介电材料中。 保险丝元件包括位于线路开口内的导电材料,该导电材料包括具有第一厚度的第一扩散阻挡层,位于侧壁上的第一厚度和线路开口的底壁。 抗熔丝元件包括位于组合的通孔和线路开口内的导电材料,其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层 第一厚度位于第一扩散阻挡层上。

    TUNGSTEN METALLIZATION: STRUCTURE AND FABRICATION OF SAME

    公开(公告)号:US20130043591A1

    公开(公告)日:2013-02-21

    申请号:US13211722

    申请日:2011-08-17

    IPC分类号: H01L23/482 H01L21/283

    摘要: A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.