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    NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES
    15.
    发明申请
    NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES 审中-公开

    公开(公告)号：US20150364207A1

    公开(公告)日：2015-12-17

    申请号：US14753500

    申请日：2015-06-29

    Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

    Inventor： Jin-Ki KIM

    IPC: G11C16/34

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

    Abstract: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

    DEVICE SELECTION SCHEMES IN MULTI CHIP PACKAGE NAND FLASH MEMORY SYSTEM
    16.
    发明申请
    DEVICE SELECTION SCHEMES IN MULTI CHIP PACKAGE NAND FLASH MEMORY SYSTEM 有权
    多芯片封装NAND闪存存储器系统中的器件选择方案

    公开(公告)号：US20140313831A1

    公开(公告)日：2014-10-23

    申请号：US14321987

    申请日：2014-07-02

    Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

    Inventor： Jin-Ki KIM

    IPC: G11C16/06

    CPC classification number: G11C15/046 ,  G11C7/109 ,  G11C8/12 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08

    Abstract: Device selection schemes in multi-chip package NAND flash memory systems are provided. A memory system is provided that has a memory controller, and a number of memory devices connected to the controller via a common bus with a multi-drop connection. The memory controller performs device selection by command. A corresponding memory controller is provided which performs device selection by command. Alternatively, device selection is performed by address. A memory device is provided use in memory system comprising a memory controller, and a number of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection. The memory device has a register containing a device identifier, and a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match. The memory device is selected if the device identifier comparator determines there is a match.

    Abstract translation: 提供了多芯片封装NAND闪速存储器系统中的器件选择方案。 提供了一种存储器系统，其具有存储器控制器以及通过具有多点连接的公共总线连接到控制器的多个存储器件。 内存控制器通过命令执行设备选择。 提供相应的存储器控​​制器，其通过命令执行设备选择。 或者，设备选择由地址执行。 在存储器系统中提供存储器装置，该存储器系统包括存储器控制器，以及包括通过具有多点连接的公共总线连接到控制器的存储器件的多个存储器件。 存储器件具有包含器件标识符的寄存器和将接收到的输入地址的选定位与寄存器的内容进行比较的器件标识符比较器，以确定是否存在匹配。 如果设备标识符比较器确定存在匹配，则选择存储器件。

    DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION
    17.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION 有权
    具有完全独立部分阵列刷新功能的动态随机访问记忆

    公开(公告)号：US20140233325A1

    公开(公告)日：2014-08-21

    申请号：US14265852

    申请日：2014-04-30

    Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

    Inventor： Jin-Ki KIM ,  HakJune OH

    IPC: G11C11/406

    CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

    Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

    Abstract translation: 动态随机存取存储器件包括多个存储器子块。 每个子块具有连接多个数据存储单元的多个字线。 部分阵列自刷新（PASR）配置设置是独立制作的。 根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。 可以选择子块地址的任何种类的组合。 因此，存储器子块被完全独立地刷新。 用于数据保留的用户可选择的存储器阵列提供有效的存储器控​​制编程，特别是对于低功率

    FLASH MEMORY SYSTEM
    18.
    发明申请
    FLASH MEMORY SYSTEM 审中-公开

    公开(公告)号：US20180329627A1

    公开(公告)日：2018-11-15

    申请号：US15976255

    申请日：2018-05-10

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Jin-Ki KIM

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

    Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

    NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
    20.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES 审中-公开
    具有多个外部电源的非易失性半导体存储器

    公开(公告)号：US20160099072A1

    公开(公告)日：2016-04-07

    申请号：US14969351

    申请日：2015-12-15

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Jin-Ki KIM ,  Peter B. GILLINGHAM

    IPC: G11C16/30 ,  G11C16/26 ,  G11C16/14

    CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

    Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

    Abstract translation: 存储器件包括诸如用于存储数据的闪存的核心存储器。 存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。 另外，存储器件包括用于接收第二电压的第二电源输入。 存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。 电源管理电路将内部电压提供或传送到闪存。 由功率管理电路（例如，电压转换器电路）产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

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