公开(公告)号：US09768371B2

公开(公告)日：2017-09-19

申请号：US14383837

申请日：2013-03-07

Applicant: D-Wave Systems Inc.

Inventor： Eric Ladizinsky ,  Jeremy P. Hilton ,  Byong Hyop Oh ,  Paul I. Bunyk

IPC: H01L39/00 ,  H01L39/24 ,  B82Y10/00 ,  H01L39/22 ,  H01L39/02 ,  H01L39/12 ,  G06N99/00 ,  H01L27/18

CPC classification number: H01L39/2493 ,  B82Y10/00 ,  G06N99/002 ,  H01L27/18 ,  H01L39/025 ,  H01L39/125 ,  H01L39/22 ,  H01L39/223 ,  H01L39/24 ,  H01L39/2406

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

公开(公告)号：US20170098682A1

公开(公告)日：2017-04-06

申请号：US15289782

申请日：2016-10-10

Applicant: D-Wave Systems Inc.

Inventor： Eric Ladizinsky ,  Geordie Rose ,  Jeremy P. Hilton ,  Eugene Dantsker ,  Byong Hyop Oh

IPC: H01L27/18 ,  G06N99/00 ,  H01L39/24 ,  H01L39/02 ,  H01L39/22

CPC classification number: H01L27/18 ,  B82Y10/00 ,  G06N99/002 ,  H01L28/24 ,  H01L39/025 ,  H01L39/223 ,  H01L39/2406 ,  H01L39/2493 ,  Y10S977/707 ,  Y10S977/723 ,  Y10S977/943

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

公开(公告)号：US20230240154A1

公开(公告)日：2023-07-27

申请号：US18010283

申请日：2021-06-22

Applicant: D-WAVE SYSTEMS INC.

Inventor： Byong Hyop Oh ,  Eric G. Ladizinsky ,  J. Jason Yao

IPC: H10N60/01 ,  H10N60/80

CPC classification number: H10N60/01 ,  H10N60/80

Abstract: Methods of forming superconducting integrated circuits are discussed. The method includes depositing a first superconducting metal layer to overlie at least a portion of a substrate, depositing a dielectric layer to cover a first region of the first superconducting metal layer, pattering the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and form an opening, and depositing a second superconducting metal layer at an ambient temperature that is less than a melting temperature of the second superconducting metal layer such that the second superconducting metal layer fills the opening and conductively contacts the at least a portion of the first region of the first superconducting metal layer.

公开(公告)号：US20220263007A1

公开(公告)日：2022-08-18

申请号：US17681303

申请日：2022-02-25

Applicant: D-WAVE SYSTEMS INC.

Inventor： Trevor M. Lanting ,  Danica W. Marsden ,  Byong Hyop Oh ,  Eric G. Ladizinsky ,  Shuiyuan Huang ,  J. Jason Yao ,  Douglas P. Stadtler

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/22 ,  H01L39/24

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

公开(公告)号：US10991755B2

公开(公告)日：2021-04-27

申请号：US16569221

申请日：2019-09-12

Applicant: D-WAVE SYSTEMS INC.

Inventor： Eric Ladizinsky ,  Geordie Rose ,  Jeremy P. Hilton ,  Eugene Dantsker ,  Byong Hyop Oh

IPC: H01L27/18 ,  G06N10/00 ,  B82Y10/00 ,  H01L39/22 ,  H01L39/24 ,  H01L49/02 ,  H01L39/02

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

公开(公告)号：US10454015B2

公开(公告)日：2019-10-22

申请号：US15503367

申请日：2015-08-12

Applicant: D-Wave Systems Inc.

Inventor： Trevor Michael Lanting ,  Eric G. Ladizinsky ,  J. Jason Yao ,  Byong Hyop Oh

IPC: H01L39/24 ,  H01L27/18 ,  H01L39/22 ,  H01L21/768 ,  H01L23/532

Abstract: Fabricating wiring layers above a Josephson junction multi-layer may include removing a part of the multilayer; depositing an insulating layer to overlie a part of the multilayer; and patterning the insulating layer to define a hole in the insulating layer. The method includes depositing a first superconducting wiring layer over a part of the insulating layer and within a portion of the hole. Further, insulating and wiring layers may be deposited and a topmost wiring layer defined. The method includes depositing a passivating layer to overlie the topmost wiring layer. Fabricating a superconducting integrated circuit comprising a hybrid dielectric system may include depositing a high-quality dielectric layer that overlies a superconducting feature. The method includes depositing a second dielectric layer that overlies at least part of the high-quality dielectric layer. The second dielectric layer can comprise a conventional dielectric material.

公开(公告)号：US20180308896A1

公开(公告)日：2018-10-25

申请号：US15956404

申请日：2018-04-18

Applicant: D-Wave Systems Inc.

Inventor： Eric Ladizinsky ,  Geordie Rose ,  Jeremy P. Hilton ,  Eugene Dantsker ,  Byong Hyop Oh

IPC: H01L27/18 ,  G06N99/00 ,  B82Y10/00 ,  H01L39/24 ,  H01L49/02 ,  H01L39/02 ,  H01L39/22

CPC classification number: H01L27/18 ,  B82Y10/00 ,  G06N10/00 ,  H01L28/24 ,  H01L39/025 ,  H01L39/223 ,  H01L39/2406 ,  H01L39/2493 ,  Y10S977/707 ,  Y10S977/723 ,  Y10S977/943

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

公开(公告)号：US20200152851A1

公开(公告)日：2020-05-14

申请号：US16681431

申请日：2019-11-12

Applicant: D-WAVE SYSTEMS INC.

Inventor： Trevor M. Lanting ,  Danica W. Marsden ,  Byong Hyop Oh ,  Eric G. Ladizinsky ,  Shuiyuan Huang ,  J. Jason Yao ,  Douglas P. Stadtler

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/24 ,  H01L39/22

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

公开(公告)号：US20200006421A1

公开(公告)日：2020-01-02

申请号：US16569221

申请日：2019-09-12

Applicant: D-WAVE SYSTEMS INC.

Inventor： Eric Ladizinsky ,  Geordie Rose ,  Jeremy P. Hilton ,  Eugene Dantsker ,  Byong Hyop Oh

IPC: H01L27/18 ,  G06N10/00 ,  B82Y10/00 ,  H01L39/22 ,  H01L39/24 ,  H01L49/02 ,  H01L39/02

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

公开(公告)号：US10453894B2

公开(公告)日：2019-10-22

申请号：US15956404

申请日：2018-04-18

Applicant: D-Wave Systems Inc.

Inventor： Eric Ladizinsky ,  Geordie Rose ,  Jeremy P. Hilton ,  Eugene Dantsker ,  Byong Hyop Oh

IPC: H01L27/18 ,  G06N10/00 ,  B82Y10/00 ,  H01L39/22 ,  H01L39/24 ,  H01L49/02 ,  H01L39/02

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.