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    Miniature digital assistant having enhanced host communication
    13.
    发明授权
    Miniature digital assistant having enhanced host communication 失效
    具有增强的主机通信的微型数字助理

    公开(公告)号：US5835732A

    公开(公告)日：1998-11-10

    申请号：US144231

    申请日：1993-10-28

    Applicant: Dan Kikinis ,  Pascal Dornier ,  William J. Seiler

    Inventor： Dan Kikinis ,  Pascal Dornier ,  William J. Seiler

    IPC: G06F1/26 ,  G06F1/00 ,  G06F1/16 ,  G06F1/20 ,  G06F3/033 ,  G06F3/048 ,  G06F13/40 ,  G06F15/02 ,  G06F21/00 ,  G06F21/22 ,  H04M1/247 ,  H04M1/275 ,  H04M1/725 ,  H04M3/42 ,  H04M11/06 ,  H04N1/00 ,  H04N1/195 ,  H04Q7/32 ,  H05K5/02 ,  G06F3/00 ,  G06F13/00

    CPC classification number: G06F1/1632 ,  G06F1/1626 ,  G06F1/1656 ,  G06F1/203 ,  G06F1/206 ,  G06F13/409 ,  G06F15/0225 ,  G06F21/62 ,  G06F3/0482 ,  H04M1/275 ,  H04M1/725 ,  H04M1/72533 ,  H04M11/06 ,  H04M3/42314 ,  H05K5/0273 ,  H04M1/2473 ,  H04M3/42323

    Abstract: A miniature digital assistant module with a local CPU, a memory, and a touchscreen I/O interface in a preferred embodiment, has a host interface comprising a full-service parallel bus, including data lines, address lines, read/write signals, and at least one memory control signal, connected to the local CPU and also to a connector at a surface of the personal digital assistant. The full-service bus connection provides direct bus communication between the personal digital assistant and a host computer. In a preferred embodiment, the miniature digital assistant also stores a security code, which the host can recognize. The miniature digital assistant forms a host/satellite combination with the host computer, which has a docking bay. When the miniature digital assistant is docked, a docking control routine controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In an alternative embodiment the personal digital assistant also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port, even while the miniature digital assistant is docked.

    Abstract translation: 具有本地CPU，存储器和触摸屏I / O接口的微型数字助理模块在优选实施例中具有主机接口，其包括全业务并行总线，包括数据线，地址线，读/写信号和 至少一个存储器控制信号，连接到本地CPU并且还连接到个人数字助理的表面处的连接器。 全业务总线连接提供个人数字助理和主机之间的直接总线通信。 在优选实施例中，微型数字助理还存储主机可以识别的安全码。 微型数字助理与主机形成主机/卫星组合，主机具有坞站。 当小型数字助理被对接时，对接控制例程基于用户向主机提供的一个或多个密码来控制主机对个人数字助理的存储器的访问。 在替代实施例中，个人数字助理还具有连接到本地CPU的扩展端口，并且扩展外围设备可以通过扩展端口连接和操作，即使在微型数字助理被对接时也是如此。

    Personal digital assistant module having a broadcast pointer device
    14.
    发明授权
    Personal digital assistant module having a broadcast pointer device 失效
    具有广播指针装置的个人数字助理模块

    公开(公告)号：US5822230A

    公开(公告)日：1998-10-13

    申请号：US676899

    申请日：1996-07-08

    Applicant: Dan Kikinis ,  Pascal Dornier ,  William J. Seiler

    Inventor： Dan Kikinis ,  Pascal Dornier ,  William J. Seiler

    IPC: G06F1/16 ,  G06F3/02 ,  G06F3/033 ,  G06F3/043 ,  G06F3/048 ,  G06F1/00

    CPC classification number: G06F1/169 ,  G06F1/1616 ,  G06F1/1632 ,  G06F1/1688 ,  G06F1/1698 ,  G06F3/0213 ,  G06F3/0354 ,  G06F3/03541 ,  G06F3/03549 ,  G06F3/0485 ,  G06F2211/007 ,  G06F2211/1097

    Abstract: A personal digital assistant module with a local CPU, (central processing unit) memory, and I/O (input/output) interface has a host interface comprising a bus connected to the local CPU and a connector at a surface of the personal digital assistant for interfacing to a bus connector of a host general-purpose computer, providing direct bus communication between the personal digital assistant and the host general-purpose computer. In an embodiment, the personal digital assistant also stores a security code. The personal digital assistant according to the invention forms a host/satellite combination with a host computer having a docking bay, wherein upon docking a docking protocol controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In another embodiment the personal digital assistant also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port. Connectable devices may include input devices such as pointer devices, that may in some cases be stored in a compartment fashioned for the purpose in the personal digital assistant.

    Abstract translation: 具有本地CPU（中央处理单元）存储器和I / O（输入/输出）接口的个人数字助理模块具有包括连接到本地CPU的总线的主机接口和个人数字助理的表面处的连接器 用于连接到主机通用计算机的总线连接器，在个人数字助理和主机通用计算机之间提供直接总线通信。 在一个实施例中，个人数字助理还存储安全码。 根据本发明的个人数字助理与具有对接间隔的主计算机形成主机/卫星组合，其中在对接时，对接协议基于由个人数字助理提供的一个或多个密码来控制主机对个人数字助理的存储器的访问 用户到主机。 在另一个实施例中，个人数字助理还具有连接到本地CPU的扩展端口，并且扩展外围设备可以通过扩展端口连接和操作。 可连接设备可以包括诸如指示器设备的输入设备，其可以在某些情况下被存储在为个人数字助理中的目的而​​设计的隔间中。

    Personal organizer with interface for recording digital voice files
    15.
    发明授权
    Personal organizer with interface for recording digital voice files 失效
    具有记录数字语音文件接口的个人组织者

    公开(公告)号：US5812870A

    公开(公告)日：1998-09-22

    申请号：US755247

    申请日：1996-11-22

    Applicant: Dan Kikinis ,  Pascal Dornier ,  William J. Seiller

    Inventor： Dan Kikinis ,  Pascal Dornier ,  William J. Seiller

    IPC: H04M1/65 ,  H04M1/72 ,  G06F15/76

    CPC classification number: H04M1/65 ,  H04M1/6505 ,  H04M1/72

    Abstract: A digital assistant computer device has an audio input interface and a memory adapted to receive audio input of significant time extent, and to convert the input and store it as a digital sound file. The digital assistant in one embodiment has a CPU and bus, input and display apparatus, on-board memory, and a microphone and digital signal processor for accepting and converting audio input. In some such embodiments the on-board memory is flash memory

    Abstract translation: 数字助理计算机设备具有音频输入接口和适于接收有效时间范围的音频输入的存储器，并且将输入转换并将其存储为数字声音文件。 一个实施例中的数字助理具有CPU和总线，输入和显示装置，板上存储器，以及用于接收和转换音频输入的麦克风和数字信号处理器。 在一些这样的实施例中，车载存储器是闪存

    Variable-voltage CPU voltage regulator
    17.
    发明授权
    Variable-voltage CPU voltage regulator 失效

    公开(公告)号：US5774734A

    公开(公告)日：1998-06-30

    申请号：US753262

    申请日：1996-11-12

    Applicant: Dan Kikinis ,  Pascal Dornier

    Inventor： Dan Kikinis ,  Pascal Dornier

    IPC: H02M3/155 ,  G05F1/46 ,  G06F1/26

    CPC classification number: G05F1/465 ,  G06F1/26

    Abstract: An integrated CPU has an on-board switching voltage regulator with an electrically-erasable programmable read-only memory electronically accessible for storing a feedback reference coefficient for control. In further embodiments, output voltage is tuned via a second EEPROM storing an electronically accessible value in concert with a solid-state resistor ladder. In other embodiments, signals on interrupt lines to the CPU are monitored to provide a prewarning of impending activity by the CPU requiring dramatically increased current flow. In yet other embodiments, solid state circuitry is provided to reduce or eliminate capacitors used for dealing with input current surges to the CPU.

    Disk array controller with enhanced synchronous write
    20.
    发明授权
    Disk array controller with enhanced synchronous write 失效
    磁盘阵列控制器具有增强的同步写入功能

    公开(公告)号：US5835955A

    公开(公告)日：1998-11-10

    申请号：US918782

    申请日：1997-08-25

    Applicant: Pascal Dornier ,  Dan Kikinis

    Inventor： Pascal Dornier ,  Dan Kikinis

    IPC: G06F11/14 ,  G06F12/08 ,  G06F12/16

    CPC classification number: G06F11/1435 ,  G06F12/0866

    Abstract: A disk array server has a cache and a log drive wherein data blocks, as received are written synchronously to both the cache and the log drive, the cache being written back to the disk array as opportunity affords. The log drive is managed so, when full, data is overwritten in the order first stored on the log drive. Data blocks written to the log drive are flagged as to whether the same block in cache has been written to the disk array, and the flags are updated as the cache is written back to the disk array. In the event of a power failure, data lost from the volatile cache as not yet written to the disk array may be recovered from the log drive. In one embodiment, the recovery is automatic on startup after a power failure.

    Abstract translation: 磁盘阵列服务器具有高速缓存和日志驱动器，其中所接收的数据块与高速缓存和日志驱动器同时写入，高速缓存作为机会提供被写回到磁盘阵列。 日志驱动器被管理，所以当完整时，数据将以先前存储在日志驱动器上的顺序覆盖。 写入到日志驱动器的数据块被标记为高速缓存中的相同块是否已写入磁盘阵列，并且当高速缓存写回到磁盘阵列时，标志被更新。 在电源故障的情况下，可能会从日志驱动器恢复从易失性缓存中丢失的尚未写入磁盘阵列的数据。 在一个实施例中，恢复在电源故障后的启动时是自动的。

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