公开(公告)号：US20090161433A1

公开(公告)日：2009-06-25

申请号：US11961871

申请日：2007-12-20

申请人： Dana Lee ,  Nima Mokhlesi ,  Deepak Chandra Sekar

发明人： Dana Lee ,  Nima Mokhlesi ,  Deepak Chandra Sekar

IPC分类号： G11C16/10 ,  G11C16/26

CPC分类号： G11C16/30

摘要： Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.

摘要翻译： 提出用于处理可能的源极偏置的技术是由非易失性存储器的读/写电路的接地回路中的非零电阻引入的误差。 误差是由电流流动时芯片地线源极电阻的电压降引起的。 为此，存储器件包括源极电位调节电路，其包括有源电路元件，该有源电路元件具有连接到参考电压的第一输入端，并且具有连接到反馈回路的第二输入端，该反馈回路可连接到汇集节点，存储器单元 的结构块现在已经跑到地面上了。 变化包括可在聚集节点和地之间连接的非线性电阻元件。

公开(公告)号：US07544569B2

公开(公告)日：2009-06-09

申请号：US11516431

申请日：2006-09-05

申请人： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

发明人： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/42336 ,  G11C16/0425 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328

摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。 多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。 多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。 每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。 多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。 每个选择门位于一对浮动门之间。

公开(公告)号：US20090016113A1

公开(公告)日：2009-01-15

申请号：US11775851

申请日：2007-07-10

申请人： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

发明人： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

IPC分类号： G11C16/06 ,  H01L29/788 ,  G11C16/16

CPC分类号： G11C16/0458 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7887

摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

摘要翻译： 公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。 多个浮动栅极彼此间隔开并且与沟道区域绝缘。 多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。 多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。 通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

公开(公告)号：US07439572B2

公开(公告)日：2008-10-21

申请号：US11303567

申请日：2005-12-15

申请人： Bomy Chen ,  Hieu Van Tran ,  Dana Lee ,  Jack Edward Frayer

发明人： Bomy Chen ,  Hieu Van Tran ,  Dana Lee ,  Jack Edward Frayer

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7885

摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injecton from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.

摘要翻译： 堆叠式非易失性存储器浮栅器件具有控制栅极。 通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。 擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。 最后，为了增加密度，可以在沟槽中制造每个单元。

公开(公告)号：US07399678B2

公开(公告)日：2008-07-15

申请号：US11292557

申请日：2005-12-02

申请人： Dana Lee ,  Bomy Chen

发明人： Dana Lee ,  Bomy Chen

IPC分类号： H01L21/8234

CPC分类号： H01L27/11266 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/112

摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

公开(公告)号：US20080151628A1

公开(公告)日：2008-06-26

申请号：US11614884

申请日：2006-12-21

申请人： Dana Lee ,  Jeffrey Lutze

发明人： Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： System for programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).

摘要翻译： 用于通过从注入存储器单元的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程的系统，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到所选位线的漏极节点 门节点与下一个相邻字线WL（n-1）耦合到字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

公开(公告)号：US07307308B2

公开(公告)日：2007-12-11

申请号：US10797296

申请日：2004-03-09

申请人： Dana Lee ,  Bomy Chen ,  Sohrab Kianian

发明人： Dana Lee ,  Bomy Chen ,  Sohrab Kianian

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

摘要： A buried bit line read/program non-volatile memory cell and array is capable of achieving high density. The cell and array is made in a semiconductor substrate which has a plurality of spaced apart trenches, with a planar surface between the trenches. Each trench has a side wall and a bottom wall. Each memory cell has a floating gate for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having two portions. One of the source/drain regions is in the bottom wall of the trench. The floating gate is in the trench and is is over a first portion of the channel and is spaced apart from the side wall of the trench. A gate electrode controls the conduction of the channel in the second portion, which is in the planar surface of the substrate. The other source/drain region is in the substrate in the planar surface of the substrate. An independently controllable control gate is also in the trench, insulated from the floating gate and is capacitively coupled thereto. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode or from the floating gate to the source/drain region at the bottom wall of the trench. The source, drain and control gates are all substantially parallel to one another, with the gate electrode substantially perpendicular to the source/drain/control gates. The source/drain lines are buried in the substrate, creating a virtual ground array.

摘要翻译： 掩埋位线读/程序非易失性存储单元和阵列能够实现高密度。 电池和阵列由具有多个间隔开的沟槽的半导体衬底制成，沟槽之间具有平坦表面。 每个沟槽都有一个侧壁和一个底壁。 每个存储单元具有用于存储其上的电荷的浮动栅极。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有两个部分。 源/漏区中的一个位于沟槽的底壁。 浮动栅极在沟槽中，并且在沟槽的第一部分之上并且与沟槽的侧壁间隔开。 栅电极控制在衬底的平面中的第二部分中的沟道的导通。 另一个源极/漏极区域位于衬底的平面表面中的衬底中。 独立可控的控制栅极也在沟槽中，与浮动栅极绝缘并且与其电容耦合。 通过热通道电子注入的电池程序，并且通过Fowler-Nordheim将电子从浮栅隧穿到栅电极或从浮栅到沟槽底壁处的源极/漏极区擦除。 源极，漏极和控制栅极都基本上彼此平行，栅电极基本上垂直于源极/漏极/控制栅极。 源极/漏极线被埋在衬底中，形成虚拟接地阵列。

公开(公告)号：US20070237005A1

公开(公告)日：2007-10-11

申请号：US11810714

申请日：2007-06-06

申请人： Yuniarto Widjaja ,  John Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

发明人： Yuniarto Widjaja ,  John Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/0425 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3431 ,  G11C2216/18 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括在衬底中具有第二导电类型的第二区域的第二导电类型的第一区域，与第一区域间隔开。 在第一区域和第二区域之间限定连续的第一通道区域。 多个浮动栅极彼此间隔开，每个浮置栅极位于沟道区域的独立部分上。 设置有多个控制栅极，每个与浮动栅极相关联并与其相邻。 每个控制栅极具有两个部分：沟道区域的一部分上的第一部分和相关联的浮动栅极上的第二部分，并与其电容耦合。

公开(公告)号：US20070210369A1

公开(公告)日：2007-09-13

申请号：US11375386

申请日：2006-03-13

申请人： Bomy Chen ,  Yaw Hu ,  Dana Lee

发明人： Bomy Chen ,  Yaw Hu ,  Dana Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324

摘要： A non-volatile floating gate memory cell, having a single polysilicon gate, compatible with conventional logic processes, comprises a substrate of a first conductivity type. A first and a second region of a second conductivity type are in the substrate, spaced apart from one another to define a channel region therebetween. A first gate is insulated from the substrate and is positioned over a first portion of the channel region and over the first region and is substantially capacitively coupled thereto. A second gate is insulated from the substrate, and is spaced apart from the first gate and is positioned over a second portion of the channel region, different from the first portion, and has little or no overlap with the second region.

摘要翻译： 具有与常规逻辑处理兼容的单个多晶硅栅极的非易失性浮动栅极存储单元包括第一导电类型的衬底。 第二导电类型的第一和第二区域在衬底中，彼此间隔开以限定它们之间的沟道区域。 第一栅极与衬底绝缘并且被定位在沟道区域的第一部分上方并且超过第一区域并且基本上电容耦合到其上。 第二栅极与衬底绝缘，并且与第一栅极间隔开并且位于与第一部分不同的沟道区域的第二部分上方，并且与第二区域几乎没有或没有重叠。

公开(公告)号：US07242050B2

公开(公告)日：2007-07-10

申请号：US10714243

申请日：2003-11-13

申请人： Bomy Chen ,  Hieu Van Tran ,  Dana Lee ,  Jack Edward Frayer

发明人： Bomy Chen ,  Hieu Van Tran ,  Dana Lee ,  Jack Edward Frayer

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7885

摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.

摘要翻译： 堆叠式非易失性存储器浮栅器件具有控制栅极。 通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。 擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。 最后，为了增加密度，可以在沟槽中制造每个单元。