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    Field programmable gate array having internal logic transistors with two different gate insulator thicknesses
    11.
    发明授权
    Field programmable gate array having internal logic transistors with two different gate insulator thicknesses 失效
    具有两个不同栅极绝缘体厚度的内部逻辑晶体管的现场可编程门阵列

    公开(公告)号：US6127845A

    公开(公告)日：2000-10-03

    申请号：US112700

    申请日：1998-07-08

    申请人： Paige A. Kolze ,  Andre Stolmeijer ,  David D. Eaton

    发明人： Paige A. Kolze ,  Andre Stolmeijer ,  David D. Eaton

    IPC分类号： H01L21/8234 ,  H01L27/118 ,  H01L25/00 ,  G06F7/38

    CPC分类号： H01L21/823462 ,  H01L27/11807

    摘要： In a programmable device employing antifuses, first digital logic transistors the gates of which will experience a programming voltage Vpp have a greater gate insulator thickness than do second digital logic transistors the gates of which will not experience the programming voltage. The first digital logic transistors may be logic module input device transistors. The first digital logic transistors may be transistors coupled to an enable input lead where the enable input lead is couplable to a tie-high conductor or to a tie-low conductor depending on which of two antifuses is programmed.

    摘要翻译： 在采用反熔丝的可编程器件中，其栅极经历编程电压Vpp的第一数字逻辑晶体管具有比其门不会经历编程电压的第二数字逻辑晶体管更大的栅绝缘体厚度。 第一数字逻辑晶体管可以是逻辑模块输入器件晶体管。 第一数字逻辑晶体管可以是耦合到使能输入引线的晶体管，其中根据两个反熔丝中的哪一个被编程，使能输入引线可以连接到连接导体或连接低导体。

    Programming architecture for field programmable gate array
    13.
    发明授权
    Programming architecture for field programmable gate array 有权
    现场可编程门阵列编程架构

    公开(公告)号：US06169416A

    公开(公告)日：2001-01-02

    申请号：US09145581

    申请日：1998-09-01

    申请人： David D. Eaton ,  Paige A. Kolze

    发明人： David D. Eaton ,  Paige A. Kolze

    IPC分类号： H03K19173

    CPC分类号： H03K19/17748 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

    摘要： The programmable logic of a programmable device is sectioned into four logic regions. Each logic region includes logic elements and a programmable interconnect structure employing antifuses for programmably interconnecting selected ones of those logic elements. Programming conductors for supplying programming current to antifuses of a logic region extend across the logic region but do not extend across other logic regions. Similarly, programming control conductors that control programming transistors of the logic region extend across the logic region but do not extend across other logic regions. The programmable device structure allows four antifuses to be programmed simultaneously, one antifuse in each logic region. An antifuse can be selected for simultaneous programming from a logic region, irrespective of the other three antifuses that are or may be selected for simultaneous programming from the other three logic regions. Four programming current multiplexers and four programming buses are provided for each logic region so that the programming current that programs each antifuse flows from a separate input terminal. The resistance of the programming conductors is reduced by the use of parallel strips of metal in multiple metal layers.

    摘要翻译： 可编程器件的可编程逻辑被分为四个逻辑区域。 每个逻辑区域包括逻辑元件和采用反熔丝的可编程互连结构，以可编程地互连那些逻辑元件中的选定的逻辑元件。 用于向逻辑区域的反熔点提供编程电流的编程导体跨越逻辑区域延伸，但不延伸到其他逻辑区域。 类似地，控制逻辑区域的编程晶体管的编程控制导体跨越逻辑区域延伸，但不跨越其它逻辑区域延伸。 可编程器件结构允许在每个逻辑区域中同时编程四个反熔丝，一个反熔丝。 可以选择反熔丝以用于从逻辑区域进行同时编程，而不管其他三个反熔丝是否来自其他三个逻辑区域也可以被选择用于同时编程。 为每个逻辑区域提供四个编程电流复用器和四个编程总线，使得编程每个反熔丝的编程电流从单独的输入端子流出。 通过在多个金属层中使用平行的金属条来减少编程导体的电阻。

    Protection of logic modules in a field programmable gate array during antifuse programming
    14.
    发明授权
    Protection of logic modules in a field programmable gate array during antifuse programming 失效
    在反熔丝编程期间保护现场可编程门阵列中的逻辑模块

    公开(公告)号：US6157207A

    公开(公告)日：2000-12-05

    申请号：US76367

    申请日：1998-05-11

    申请人： David D. Eaton ,  Sudarshan Varshney ,  Paige A. Kolze

    发明人： David D. Eaton ,  Sudarshan Varshney ,  Paige A. Kolze

    IPC分类号： H01L21/8234 ,  H01L27/118 ,  G06F7/38 ,  H03K19/177

    CPC分类号： H01L27/11807 ,  H01L21/823462

    摘要： To protect logic module output devices from high voltages, logic modules are not powered during antifuse programming. In some embodiments, two separate power input terminals VCC1 and VCC2 are provided: power input terminal VCC1 being coupled to power the logic modules, and power input terminal VCC2 being coupled to power the programming control circuitry. Power terminal VCC1 is left floating or is grounded during antifuse programming such that the logic modules are not powered but such that the programming circuitry is powered during antifuse programming via the second power terminal VCC2. Logic module output protection transistors are not required nor is the associated charge pump. Because the logic module input devices are not powered, a current surge through the input devices on power up does not occur and an internal disable signal and associated circuitry is not required. In one embodiment, the field programmable gate array is made smaller because it has no internal disable signal and associated circuitry, no logic module output protection transistors, and no charge pump that operates during normal circuit operation. In embodiments, power input terminal VCC2 is a high voltage compatible power input terminal.

    摘要翻译： 为了保护逻辑模块输出设备免受高电压的影响，逻辑模块在反熔丝编程期间未通电。 在一些实施例中，提供两个单独的电源输入端子VCC1和VCC2：电源输入端子VCC1被耦合以对逻辑模块供电，并且电源输入端子VCC2被耦合以对编程控制电路供电。 电源端子VCC1在反熔丝编程期间处于悬空状态或接地状态，使得逻辑模块未通电，而使编程电路在反熔丝编程期间通过第二电源端子VCC2供电。 不需要逻辑模块输出保护晶体管，也不需要相关的电荷泵。 由于逻辑模块输入设备未通电，所以不会在上电时通过输入设备产生电流浪涌，并且不需要内部禁用信号和相关电路。 在一个实施例中，由于现场可编程门阵列没有内部禁用信号和相关联的电路，没有逻辑模块输出保护晶体管，并且没有在正常电路操作期间操作的电荷泵，所以现场可编程门阵列被制造得更 在实施例中，电源输入端子VCC2是高电压兼容电力输入端子。

    Clock network for field programmable gate array
    15.
    发明授权
    Clock network for field programmable gate array 失效
    现场可编程门阵列的时钟网络

    公开(公告)号：US5892370A

    公开(公告)日：1999-04-06

    申请号：US781985

    申请日：1997-01-03

    申请人： David D. Eaton ,  Mukesh T. Lulla ,  Ker-Ching Liu

    发明人： David D. Eaton ,  Mukesh T. Lulla ,  Ker-Ching Liu

    IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177 ,  H03K7/38 ,  H03K19/00

    CPC分类号： H03K17/223 ,  H03K19/177

    摘要： A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to be driven from the clock pad. An output of a selected logic cell can be coupled to the first clock bus if the clock network is to be driven from a logic cell. To increase speed of the clock network, the first clock bus is segmented (in one embodiment, collinearly extending segments can be selectively coupled together via selectively programmable antifuses) so that only a short piece of the first clock bus is used to couple either the pad or the logic cell to the clock network in high speed applications.

    摘要翻译： 现场可编程门阵列的时钟网络具有在第一维度上跨越芯片延伸的第一时钟总线。 如果时钟网络要从时钟焊盘驱动，则时钟焊盘可以耦合到第一个时钟总线。 如果要从逻辑单元驱动时钟网络，则所选逻辑单元的输出可以耦合到第一时钟总线。 为了增加时钟网络的速度，第一时钟总线被分段（在一个实施例中，共线延伸段可以通过有选择地可编程的反熔丝选择性地耦合在一起），使得仅使用第一时钟总线的短片来耦合焊盘 或逻辑单元到高速应用中的时钟网络。