公开(公告)号：US6127845A

公开(公告)日：2000-10-03

申请号：US112700

申请日：1998-07-08

申请人： Paige A. Kolze ,  Andre Stolmeijer ,  David D. Eaton

发明人： Paige A. Kolze ,  Andre Stolmeijer ,  David D. Eaton

IPC分类号： H01L21/8234 ,  H01L27/118 ,  H01L25/00 ,  G06F7/38

CPC分类号： H01L21/823462 ,  H01L27/11807

摘要： In a programmable device employing antifuses, first digital logic transistors the gates of which will experience a programming voltage Vpp have a greater gate insulator thickness than do second digital logic transistors the gates of which will not experience the programming voltage. The first digital logic transistors may be logic module input device transistors. The first digital logic transistors may be transistors coupled to an enable input lead where the enable input lead is couplable to a tie-high conductor or to a tie-low conductor depending on which of two antifuses is programmed.

摘要翻译： 在采用反熔丝的可编程器件中，其栅极经历编程电压Vpp的第一数字逻辑晶体管具有比其门不会经历编程电压的第二数字逻辑晶体管更大的栅绝缘体厚度。 第一数字逻辑晶体管可以是逻辑模块输入器件晶体管。 第一数字逻辑晶体管可以是耦合到使能输入引线的晶体管，其中根据两个反熔丝中的哪一个被编程，使能输入引线可以连接到连接导体或连接低导体。

公开(公告)号：US5986469A

公开(公告)日：1999-11-16

申请号：US932890

申请日：1997-09-17

申请人： David D. Eaton ,  Paige A. Kolze ,  James M. Apland

发明人： David D. Eaton ,  Paige A. Kolze ,  James M. Apland

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A programmable integrated circuit (see FIG. 9) has a plurality of L-shaped programming power buses (for example, 126, 130, 129 and 127) that extend along sides of the integrated circuit. Each L-shaped programming power bus extends along two adjacent sides of the integrated circuit such that legs of two L-shaped programming power buses extend along each of the sides. There are four pluralities of programming drivers (for example, 110, 117, 115 and 112), one plurality being associated with each of the four sides. There are also four programming current multiplexers (for example, 118, 125, 123 and 120), one associated with each of the sides. A programming driver of one of the plurality of programming drivers is selectively couplable to one of the two L-shaped programming power bus legs that extends along the associated side of the integrated circuit via the programming current multiplexer associated with that side. Additional pluralities of programming drivers and additional programming current multiplexers can be provided.

摘要翻译： 可编程集成电路（见图9）具有沿着集成电路的侧面延伸的多个L形编程电源总线（例如，126,130,129和127）。 每个L形编程电源总线沿着集成电路的两个相邻侧延伸，使得两个L形编程电源总线的脚沿着每个侧面延伸。 有四种编程驱动程序（例如，110,117,115和112），一个与四个方面中的每一个相关联。 还有四个编程电流多路复用器（例如，118,125,123和120），一个与每个侧面相关联。 多个编程驱动器之一的编程驱动器可选择性地耦合到两个L形编程功率总线支路中的一个，其经由与该侧相关联的编程电流复用器沿着集成电路的相关侧延伸。 可以提供额外的多个编程驱动器和附加的编程电流多路复用器。

公开(公告)号：US06169416A

公开(公告)日：2001-01-02

申请号：US09145581

申请日：1998-09-01

申请人： David D. Eaton ,  Paige A. Kolze

发明人： David D. Eaton ,  Paige A. Kolze

IPC分类号： H03K19173

CPC分类号： H03K19/17748 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： The programmable logic of a programmable device is sectioned into four logic regions. Each logic region includes logic elements and a programmable interconnect structure employing antifuses for programmably interconnecting selected ones of those logic elements. Programming conductors for supplying programming current to antifuses of a logic region extend across the logic region but do not extend across other logic regions. Similarly, programming control conductors that control programming transistors of the logic region extend across the logic region but do not extend across other logic regions. The programmable device structure allows four antifuses to be programmed simultaneously, one antifuse in each logic region. An antifuse can be selected for simultaneous programming from a logic region, irrespective of the other three antifuses that are or may be selected for simultaneous programming from the other three logic regions. Four programming current multiplexers and four programming buses are provided for each logic region so that the programming current that programs each antifuse flows from a separate input terminal. The resistance of the programming conductors is reduced by the use of parallel strips of metal in multiple metal layers.

摘要翻译： 可编程器件的可编程逻辑被分为四个逻辑区域。 每个逻辑区域包括逻辑元件和采用反熔丝的可编程互连结构，以可编程地互连那些逻辑元件中的选定的逻辑元件。 用于向逻辑区域的反熔点提供编程电流的编程导体跨越逻辑区域延伸，但不延伸到其他逻辑区域。 类似地，控制逻辑区域的编程晶体管的编程控制导体跨越逻辑区域延伸，但不跨越其它逻辑区域延伸。 可编程器件结构允许在每个逻辑区域中同时编程四个反熔丝，一个反熔丝。 可以选择反熔丝以用于从逻辑区域进行同时编程，而不管其他三个反熔丝是否来自其他三个逻辑区域也可以被选择用于同时编程。 为每个逻辑区域提供四个编程电流复用器和四个编程总线，使得编程每个反熔丝的编程电流从单独的输入端子流出。 通过在多个金属层中使用平行的金属条来减少编程导体的电阻。

公开(公告)号：US6157207A

公开(公告)日：2000-12-05

申请号：US76367

申请日：1998-05-11

申请人： David D. Eaton ,  Sudarshan Varshney ,  Paige A. Kolze

发明人： David D. Eaton ,  Sudarshan Varshney ,  Paige A. Kolze

IPC分类号： H01L21/8234 ,  H01L27/118 ,  G06F7/38 ,  H03K19/177

CPC分类号： H01L27/11807 ,  H01L21/823462

摘要： To protect logic module output devices from high voltages, logic modules are not powered during antifuse programming. In some embodiments, two separate power input terminals VCC1 and VCC2 are provided: power input terminal VCC1 being coupled to power the logic modules, and power input terminal VCC2 being coupled to power the programming control circuitry. Power terminal VCC1 is left floating or is grounded during antifuse programming such that the logic modules are not powered but such that the programming circuitry is powered during antifuse programming via the second power terminal VCC2. Logic module output protection transistors are not required nor is the associated charge pump. Because the logic module input devices are not powered, a current surge through the input devices on power up does not occur and an internal disable signal and associated circuitry is not required. In one embodiment, the field programmable gate array is made smaller because it has no internal disable signal and associated circuitry, no logic module output protection transistors, and no charge pump that operates during normal circuit operation. In embodiments, power input terminal VCC2 is a high voltage compatible power input terminal.

摘要翻译： 为了保护逻辑模块输出设备免受高电压的影响，逻辑模块在反熔丝编程期间未通电。 在一些实施例中，提供两个单独的电源输入端子VCC1和VCC2：电源输入端子VCC1被耦合以对逻辑模块供电，并且电源输入端子VCC2被耦合以对编程控制电路供电。 电源端子VCC1在反熔丝编程期间处于悬空状态或接地状态，使得逻辑模块未通电，而使编程电路在反熔丝编程期间通过第二电源端子VCC2供电。 不需要逻辑模块输出保护晶体管，也不需要相关的电荷泵。 由于逻辑模块输入设备未通电，所以不会在上电时通过输入设备产生电流浪涌，并且不需要内部禁用信号和相关电路。 在一个实施例中，由于现场可编程门阵列没有内部禁用信号和相关联的电路，没有逻辑模块输出保护晶体管，并且没有在正常电路操作期间操作的电荷泵，所以现场可编程门阵列被制造得更 在实施例中，电源输入端子VCC2是高电压兼容电力输入端子。

公开(公告)号：US06552410B1

公开(公告)日：2003-04-22

申请号：US09650773

申请日：2000-08-29

申请人： David D. Eaton ,  Ket-Chong Yap ,  Kevin K. Yee ,  E. Thomas Hart ,  Andrew K. Chan ,  Neal A. Palmer ,  Michael W. Dini ,  James Apland ,  Panawalge S. N. Gunaratna

发明人： David D. Eaton ,  Ket-Chong Yap ,  Kevin K. Yee ,  E. Thomas Hart ,  Andrew K. Chan ,  Neal A. Palmer ,  Michael W. Dini ,  James Apland ,  Panawalge S. N. Gunaratna

IPC分类号： H01L2200

CPC分类号： H03K19/1776 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors. The input/output terminals around the periphery and in the interface between the programmable circuit and dedicated device are tested using JTAG registers. The path of the test signal through the JTAG registers is selectable to pass around the periphery of both the programmable and dedicated devices or through the interface and around the periphery of only one of the programmable and dedicated devices.

摘要翻译： 诸如现场可编程门阵列的可编程电路以及诸如ASIC类型器件的专用器件在单个集成电路上与基于反熔丝的接口耦合在一起。 与专用设备通信的可配置非易失性存储器也位于集成电路上。 可编程电路的平台是现有可编程电路的一半，无需设计可编程电路。 可编程电路包括时钟网络，其从时钟端子以及专用器件中的时钟网络接收时钟信号。 专用器件和可编程电路之间的接口包括具有带测试电路的缓冲器的多个导体。 测试电路包括PMOS测试晶体管和NMOS测试晶体管，其允许对缓冲器进行测试而不编程耦合到导体的反熔丝。 使用JTAG寄存器测试周边和可编程电路与专用设备之间的接口中的输入/输出端子。 通过JTAG寄存器的测试信号的路径可选择通过可编程和专用设备的周边，或通过接口和仅可编程和专用设备之一的外围环绕。

公开(公告)号：US09433067B2

公开(公告)日：2016-08-30

申请号：US12587169

申请日：2009-10-03

申请人： Kamlapati Khalsa ,  Yefim Gluzman ,  Quyen Tran ,  David D. Eaton

发明人： Kamlapati Khalsa ,  Yefim Gluzman ,  Quyen Tran ,  David D. Eaton

IPC分类号： H05B41/04 ,  H05B41/392 ,  H05B37/02

CPC分类号： H05B41/046 ,  H05B37/0227 ,  H05B37/0272 ,  H05B41/392

摘要： A multi-lamp fluorescent light fixture includes a plurality of replaceable fluorescent lamp starter units. Each starter unit has a built-in microcontroller, an RF (Radio-Frequency) receiver, and communicates wirelessly with a master unit. The plurality of starter units can be wirelessly controlled to dim the multi-lamp fixture. Each starter unit receives a DIM command. Each starter unit identified as a dimmer starter unit responds to the DIM command by turning off coupled fluorescent lamps. Starter units not identified as dimmer starter units respond by leaving coupled lamps turned on, or alternatively, turning off and quickly restarting coupled lamps. Systems of existing light fixtures are retrofitted with such wireless starter units, and thereby made controllable by a master unit so that the master unit can dim the lights if room occupancy is not detected or if sufficient ambient light is available.

摘要翻译： 多灯荧光灯具包括多个可更换的荧光灯起动器单元。 每个启动器单元都有一个内置的微控制器，一个RF（射频）接收器，并与主机无线通讯。 可以无线地控制多个起动器单元以使多个灯具变暗。 每个起动器单元接收一个DIM指令。 识别为调光器起动器单元的每个启动器单元通过关闭耦合的荧光灯来响应DIM命令。 未识别为调光器起动器单元的起动器单元通过使耦合的灯导通而响应，或者替代地关闭并快速重新启动耦合的灯。 现有灯具的系统使用这种无线起动器单元进行改装，从而由主单元控制，使得如果没有检测到房间占用或者是否有足够的环境光可用，主单元可以使灯变暗。

公开(公告)号：US07898090B1

公开(公告)日：2011-03-01

申请号：US11904749

申请日：2007-09-28

申请人： David D. Eaton

发明人： David D. Eaton

IPC分类号： H01L23/48

CPC分类号： H01L23/576 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0275 ,  H05K2201/09681 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A general purpose BGA security cap includes a substrate, an integrated circuit die, and an array of bond balls. The substrate includes an anti-tamper security mesh of conductors. The bond balls include outer bond balls and inner bond balls that are fixed to the underside of the substrate. The integrated circuit drives and monitors the anti-tamper security mesh and communicates data using a serial physical interface through a subset of the inner bond balls. In one example, a user has circuitry to be protected. The user purchases the BGA security cap and fits it over the circuitry to be protected such that the integrated circuit of the security cap communicates tamper detect condition information via the serial interface to the underlying protected circuitry and causes sensitive information to be erased or a program to be halted in the event of a tamper condition.

摘要翻译： 通用BGA安全帽包括基板，集成电路管芯和粘结球阵列。 基板包括导体的防篡改安全网。 结合球包括固定到基底的下侧的外粘结球和内粘结球。 集成电路驱动和监视防篡改安全网，并使用串联物理接口通过内焊球的子集传送数据。 在一个示例中，用户具有要被保护的电路。 用户购买BGA安全帽并将其安装在要保护的电路上，使得安全帽的集成电路经由串行接口将篡改检测条件信息传送到底层保护电路，并导致敏感信息被擦除或程序 在篡改情况下停止。

公开(公告)号：US20080251906A1

公开(公告)日：2008-10-16

申请号：US11800175

申请日：2007-05-03

申请人： David D. Eaton ,  David R. Staab ,  Ruben C. Zeta

发明人： David D. Eaton ,  David R. Staab ,  Ruben C. Zeta

IPC分类号： H01L23/488 ,  H01L21/44 ,  H01L21/56

CPC分类号： H01L23/576 ,  H01L23/3128 ,  H01L23/647 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package-on-package (POP) secure module includes a BGA mesh cap, a first BGA package, and a second BGA package. The first BGA package includes a first integrated circuit (for example, a microcontroller that includes tamper detect logic). The second BGA package includes a second integrated circuit (for example, a memory). The second BGA package is piggy-back mounted to the first BGA package and the BGA mesh cap is piggy-back mounted to the second BGA package. A printed circuit board substrate member of the BGA mesh cap includes an embedded anti-tamper mesh. This mesh is connected in a protected manner within the module to the first integrated circuit. When the module is in use, a mesh embedded in an underlying printed circuit board is coupled to the BGA cap mesh so that both anti-tamper meshes are controlled by the tamper detect logic.

摘要翻译： 封装封装（POP）安全模块包括BGA网格盖，第一个BGA封装和第二个BGA封装。 第一个BGA封装包括第一个集成电路（例如，包含篡改检测逻辑的微控制器）。 第二BGA封装包括第二集成电路（例如，存储器）。 第二个BGA封装捎带安装在第一个BGA封装上，而BGA网罩则捎带安装在第二个BGA封装上。 BGA网罩的印刷电路板基板部件包括嵌入式防篡改网。 该网格以模块内的受保护方式连接到第一集成电路。 当模块使用时，嵌入底层印刷电路板的网格耦合到BGA盖网格，以便两个防篡改网格都由篡改检测逻辑控制。

公开(公告)号：US6140837A

公开(公告)日：2000-10-31

申请号：US161192

申请日：1998-09-25

申请人： David D. Eaton ,  Richard J. Wong ,  James M. Apland

发明人： David D. Eaton ,  Richard J. Wong ,  James M. Apland

IPC分类号： H01L21/8234 ,  H01L27/118 ,  H03K19/173 ,  G05F1/10 ,  H03K19/175

CPC分类号： H01L21/823462 ,  H01L27/11807

摘要： A programmable device has digital logic elements and a programmable interconnect structure employing antifuses, the antifuses being programmable to connect selected ones of the digital logic elements together. During normal circuit operation, a first power input terminal is used to power the digital logic elements with a first supply voltage received on the first power input terminal. During normal circuit operation, a second power input terminal is used to protect circuitry of the programmable device from high voltage signals that may be driven onto terminals of the programmable device by circuitry external to the programmable device. During antifuse programming, the second power input terminal is used to drive charge pumps of programming drivers and/or programming control drivers. In some embodiments, the second power input terminal receives a voltage higher than the first supply voltage during antifuse programming such that the oscillating signal that drives the charge pumps has a larger amplitude thereby allowing back bias threshold voltages of transistors in the charge pumps to be overcome, facilitating starting of the charge pumps, and/or increasing charge pump efficiency.

摘要翻译： 可编程器件具有采用反熔丝的数字逻辑元件和可编程互连结构，反熔丝是可编程的，以将选定的数字逻辑元件连接在一起。 在正常电路操作期间，使用第一电力输入端子以在第一电力输入端子上接收的第一电源电压为数字逻辑元件供电。 在正常电路操作期间，使用第二电力输入端子来保护可编程器件的电路免受可编程器件外部的电路驱动到可编程器件的端子的高电压信号。 在反熔丝编程期间，第二电源输入端用于驱动编程驱动器和/或编程控制驱动器的电荷泵。 在一些实施例中，第二电力输入端子在反熔丝编程期间接收高于第一电源电压的电压，使得驱动电荷泵的振荡信号具有较大的幅度，从而允许克服电荷泵中晶体管的反向偏置阈值电压 ，促进电荷泵的启动和/或增加电荷泵效率。

公开(公告)号：US08198142B1

公开(公告)日：2012-06-12

申请号：US12932141

申请日：2011-02-18

申请人： David D. Eaton

发明人： David D. Eaton

IPC分类号： H01L21/82

CPC分类号： H01L23/576 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0275 ,  H05K2201/09681 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A general purpose BGA security cap includes a substrate, an integrated circuit die, and an array of bond balls. The substrate includes an anti-tamper security mesh of conductors. The bond balls include outer bond balls and inner bond balls that are fixed to the underside of the substrate. The integrated circuit drives and monitors the anti-tamper security mesh and communicates data using a serial physical interface through a subset of the inner bond balls. In one example, a user has circuitry to be protected. The user purchases the BGA security cap and fits it over the circuitry to be protected such that the integrated circuit of the security cap communicates tamper detect condition information via the serial interface to the underlying protected circuitry and causes sensitive information to be erased or a program to be halted in the event of a tamper condition.

摘要翻译： 通用BGA安全帽包括基板，集成电路管芯和粘结球阵列。 基板包括导体的防篡改安全网。 结合球包括固定到基底的下侧的外粘结球和内粘结球。 集成电路驱动和监视防篡改安全网，并使用串联物理接口通过内焊球的子集传送数据。 在一个示例中，用户具有要被保护的电路。 用户购买BGA安全帽并将其安装在要保护的电路上，使得安全帽的集成电路经由串行接口将篡改检测条件信息传送到底层保护电路，并导致敏感信息被擦除或程序 在篡改情况下停止。