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11.发明授权Prefetching from dynamic random access memory to a static random access memory 有权从动态随机存取存储器预取到静态随机存取存储器公开(公告)号：US08032711B2
公开(公告)日：2011-10-04
申请号：US11644358
申请日：2006-12-22
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/3455 , G06F9/3802 , G06F9/383 , G06F12/0215 , G06F2212/6028 , Y02D10/13
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.
摘要翻译： 本发明的实施例一般涉及用于从动态随机存取存储器（DRAM）预取到静态随机存取存储器（SRAM）的系统，方法和装置。 在某些实施例中，预取逻辑接收与加载指令相关联的预取提示。 预取逻辑可以至少部分地基于预取提示来将两个或更多个高速缓存行从DRAM中的打开页面传送到SRAM。
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12.发明申请Guest Interrupt Controllers for Each Processor to Aid Interrupt Virtualization 有权每个处理器的客户中断控制器帮助中断虚拟化公开(公告)号：US20100191885A1
公开(公告)日：2010-07-29
申请号：US12611595
申请日：2009-11-03
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/45558 , G06F2009/45579
摘要： In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to receiving a first interrupt message communicating a first interrupt that is targeted at a host in the system. The second interrupt controller is configured to signal the processor for an interrupt in response to receiving a second interrupt message communicating a second interrupt that is targeted at a guest that is controlled by the host and that is executable on the processor.
摘要翻译： 在一个实施例中，系统包括处理器，耦合到处理器的第一中断控制器和耦合到处理器的第二中断控制器。 第一中断控制器被配置为响应于接收到传达针对系统中的主机的第一中断的第一中断消息来向处理器发信号通知中断。 第二中断控制器被配置为响应于接收到传达第二中断的第二中断信号而向处理器发出中断，所述第二中断消息针对由主机控制并且可在处理器上执行的客户机。
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公开(公告)号：US07692946B2
公开(公告)日：2010-04-06
申请号：US11771054
申请日：2007-06-29
申请人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
发明人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C5/025 , G11C7/1048 , H01L25/0655 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。 第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。 还公开了其他实施例。
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公开(公告)号：US09390018B2
公开(公告)日：2016-07-12
申请号：US13588622
申请日：2012-08-17
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/1016 , G06F2212/1041 , G06F2212/6028
摘要： The present invention provides a method and apparatus for using prefetch hints. One embodiment of the method includes bypassing, at a first prefetcher associated with a first cache, issuing requests to prefetch data from a number of memory addresses in a sequence of memory addresses determined by the first prefetcher. The number is indicated in a request received from a second prefetcher associated with a second cache. This embodiment of the method also includes issuing, from the first prefetcher, a request to prefetch data from a memory address subsequent to the bypassed memory addresses.
摘要翻译： 本发明提供一种使用预取提示的方法和装置。 该方法的一个实施例包括在与第一高速缓存相关联的第一预取器处旁路发出从由第一预取器确定的存储器地址序列中的多个存储器地址中预取数据的请求。 在从与第二高速缓存相关联的第二预取器接收的请求中指示该号码。 该方法的该实施例还包括从第一预取器发出在旁路存储器地址之后从存储器地址预取数据的请求。
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公开(公告)号：US09116815B2
公开(公告)日：2015-08-25
申请号：US13528302
申请日：2012-06-20
CPC分类号： G06F12/0862 , G06F2212/6024 , G06F2212/6026
摘要： The present invention provides a method and apparatus for throttling prefetch requests for a cache. One embodiment of the method includes selecting a sequence of relative addresses for prefetching data from a memory into lines of a cache in response to detecting a cache miss to a first address. The sequence of relative addresses is determined relative to the first address. This embodiment of the method also includes issuing a prefetch request for data from a memory address indicated by one of the sequence of relative addresses when at least one previous prefetch stream accessed prefetched data associated with this one of the sequence of relative addresses.
摘要翻译： 本发明提供了一种用于节流缓存的预取请求的方法和装置。 该方法的一个实施例包括从响应于检测到第一地址的高速缓存未命中而选择用于将数据从存储器预取到高速缓存行的相对地址序列。 相对地址的序列是相对于第一个地址确定的。 该方法的该实施例还包括当至少一个先前预取流访问与该相对地址序列中的一个相关联的预取数据时，从由相对地址序列之一指示的存储器地址中发出数据的预取请求。
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16.发明授权Guest interrupt controllers for each processor to aid interrupt virtualization 有权每个处理器的访客中断控制器可帮助中断虚拟化公开(公告)号：US08055827B2
公开(公告)日：2011-11-08
申请号：US12611595
申请日：2009-11-03
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/45558 , G06F2009/45579
摘要： In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to receiving a first interrupt message communicating a first interrupt that is targeted at a host in the system. The second interrupt controller is configured to signal the processor for an interrupt in response to receiving a second interrupt message communicating a second interrupt that is targeted at a guest that is controlled by the host and that is executable on the processor.
摘要翻译： 在一个实施例中，系统包括处理器，耦合到处理器的第一中断控制器和耦合到处理器的第二中断控制器。 第一中断控制器被配置为响应于接收到传达针对系统中的主机的第一中断的第一中断消息来向处理器发信号通知中断。 第二中断控制器被配置为响应于接收到传达第二中断的第二中断信号而向处理器发出中断，所述第二中断消息针对由主机控制并且可在处理器上执行的客户端。
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公开(公告)号：US20090001601A1
公开(公告)日：2009-01-01
申请号：US11771054
申请日：2007-06-29
申请人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Jeffrey P. Rupley, II , Edward A. Brekelbaum , Gabriel H. Loh , Bryan Black
发明人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Jeffrey P. Rupley, II , Edward A. Brekelbaum , Gabriel H. Loh , Bryan Black
IPC分类号： H01L23/48
CPC分类号： G11C7/18 , G11C5/025 , G11C7/1048 , H01L25/0655 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。 第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。 还公开了其他实施例。
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18.发明申请Prefetching from dynamic random access memory to a static random access memory 有权从动态随机存取存储器预取到静态随机存取存储器公开(公告)号：US20080155196A1
公开(公告)日：2008-06-26
申请号：US11644358
申请日：2006-12-22
IPC分类号： G06F12/12
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/3455 , G06F9/3802 , G06F9/383 , G06F12/0215 , G06F2212/6028 , Y02D10/13
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.
摘要翻译： 本发明的实施例一般涉及用于从动态随机存取存储器（DRAM）预取到静态随机存取存储器（SRAM）的系统，方法和装置。 在一些实施例中，预取逻辑接收与加载指令相关联的预取提示。 预取逻辑可以至少部分地基于预取提示来将两个或更多个高速缓存行从DRAM中的打开页面传送到SRAM。
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公开(公告)号：US06983356B2
公开(公告)日：2006-01-03
申请号：US10325795
申请日：2002-12-19
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F2212/502 , G06F2212/6022
摘要： A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level. Prefetches are inserted conservatively if the memory bandwidth utilization (MBU) rate is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.
摘要翻译： 从存储器件预取的方法包括确定预取缓冲器命中率（PBHR）和存储器带宽利用率（MBU）速率。 如果存储器带宽占用率（MBU）高于MBU阈值级别，并且预取缓冲区命中率（PBHR）高于PBHR阈值级别，则会大大插入预取。 如果存储器带宽占用率（MBU）高于MBU阈值级别，并且预取缓冲区命中率（PBHR）低于PBHR阈值级别，则保留预存取值。
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公开(公告)号：US5222215A
公开(公告)日：1993-06-22
申请号：US752149
申请日：1991-08-29
申请人： Norman C. Chou , Peter H. Gum , Roger E. Hough , Moon J. Kim , James C. Mazurowski , Donald W. McCauley , Casper A. Scalzi , John F. Scanlon , Leslie W. Wyman
发明人： Norman C. Chou , Peter H. Gum , Roger E. Hough , Moon J. Kim , James C. Mazurowski , Donald W. McCauley , Casper A. Scalzi , John F. Scanlon , Leslie W. Wyman
CPC分类号： G06F9/4812
摘要： A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.
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