公开(公告)号：US08032711B2

公开(公告)日：2011-10-04

申请号：US11644358

申请日：2006-12-22

申请人： Bryan Black ,  Murali M. Annavaram ,  Donald W. McCauley ,  John P. Devale

发明人： Bryan Black ,  Murali M. Annavaram ,  Donald W. McCauley ,  John P. Devale

IPC分类号： G06F12/06 ,  G06F13/16

CPC分类号： G06F12/0862 ,  G06F9/30043 ,  G06F9/3455 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0215 ,  G06F2212/6028 ,  Y02D10/13

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.

摘要翻译： 本发明的实施例一般涉及用于从动态随机存取存储器（DRAM）预取到静态随机存取存储器（SRAM）的系统，方法和装置。 在某些实施例中，预取逻辑接收与加载指令相关联的预取提示。 预取逻辑可以至少部分地基于预取提示来将两个或更多个高速缓存行从DRAM中的打开页面传送到SRAM。

公开(公告)号：US20080155196A1

公开(公告)日：2008-06-26

申请号：US11644358

申请日：2006-12-22

申请人： Bryan Black ,  Murali M. Annavaram ,  Donald W. McCauley ,  John P. Devale

发明人： Bryan Black ,  Murali M. Annavaram ,  Donald W. McCauley ,  John P. Devale

IPC分类号： G06F12/12

CPC分类号： G06F12/0862 ,  G06F9/30043 ,  G06F9/3455 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0215 ,  G06F2212/6028 ,  Y02D10/13

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.

摘要翻译： 本发明的实施例一般涉及用于从动态随机存取存储器（DRAM）预取到静态随机存取存储器（SRAM）的系统，方法和装置。 在一些实施例中，预取逻辑接收与加载指令相关联的预取提示。 预取逻辑可以至少部分地基于预取提示来将两个或更多个高速缓存行从DRAM中的打开页面传送到SRAM。

公开(公告)号：US08059441B2

公开(公告)日：2011-11-15

申请号：US12709620

申请日：2010-02-22

申请人： Mohammed H. Taufique ,  Derwin Jallice ,  Donald W. McCauley ,  John P. DeVale ,  Edward A. Brekelbaum ,  Jeffrey P. Rupley, II ,  Gabriel H. Loh ,  Bryan Black

发明人： Mohammed H. Taufique ,  Derwin Jallice ,  Donald W. McCauley ,  John P. DeVale ,  Edward A. Brekelbaum ,  Jeffrey P. Rupley, II ,  Gabriel H. Loh ,  Bryan Black

IPC分类号： G11C5/06

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/1048 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。 第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。 还公开了其他实施例。

公开(公告)号：US20100149849A1

公开(公告)日：2010-06-17

申请号：US12709620

申请日：2010-02-22

申请人： Mohammed Taufique ,  Derwin Jallice ,  Donald W. McCauley ,  John P. DeVale ,  Edward A. Brekelbaum ,  Jeffrey P. Rupley, II ,  Gabriel H. Loh ,  Bryan Black

发明人： Mohammed Taufique ,  Derwin Jallice ,  Donald W. McCauley ,  John P. DeVale ,  Edward A. Brekelbaum ,  Jeffrey P. Rupley, II ,  Gabriel H. Loh ,  Bryan Black

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/1048 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。 第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。 还公开了其他实施例。

公开(公告)号：US07692946B2

公开(公告)日：2010-04-06

申请号：US11771054

申请日：2007-06-29

申请人： Mohammed H. Taufique ,  Derwin Jallice ,  Donald W. McCauley ,  John P. DeVale ,  Edward A. Brekelbaum ,  Jeffrey P. Rupley, II ,  Gabriel H. Loh ,  Bryan Black

发明人： Mohammed H. Taufique ,  Derwin Jallice ,  Donald W. McCauley ,  John P. DeVale ,  Edward A. Brekelbaum ,  Jeffrey P. Rupley, II ,  Gabriel H. Loh ,  Bryan Black

IPC分类号： G11C5/06

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/1048 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。 第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。 还公开了其他实施例。

公开(公告)号：US20090001601A1

公开(公告)日：2009-01-01

申请号：US11771054

申请日：2007-06-29

申请人： Mohammed H. Taufique ,  Derwin Jallice ,  Donald W. McCauley ,  John P. DeVale ,  Jeffrey P. Rupley, II ,  Edward A. Brekelbaum ,  Gabriel H. Loh ,  Bryan Black

发明人： Mohammed H. Taufique ,  Derwin Jallice ,  Donald W. McCauley ,  John P. DeVale ,  Jeffrey P. Rupley, II ,  Edward A. Brekelbaum ,  Gabriel H. Loh ,  Bryan Black

IPC分类号： H01L23/48

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/1048 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。 第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。 还公开了其他实施例。

公开(公告)号：US20140052927A1

公开(公告)日：2014-02-20

申请号：US13588622

申请日：2012-08-17

申请人： Donald W. McCauley ,  Stephen P. Thompson

发明人： Donald W. McCauley ,  Stephen P. Thompson

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/6028

摘要： The present invention provides a method and apparatus for using prefetch hints. One embodiment of the method includes bypassing, at a first prefetcher associated with a first cache, issuing requests to prefetch data from a number of memory addresses in a sequence of memory addresses determined by the first prefetcher. The number is indicated in a request received from a second prefetcher associated with a second cache. This embodiment of the method also includes issuing, from the first prefetcher, a request to prefetch data from a memory address subsequent to the bypassed memory addresses.

摘要翻译： 本发明提供一种使用预取提示的方法和装置。 该方法的一个实施例包括在与第一高速缓存相关联的第一预取器处旁路发出从由第一预取器确定的存储器地址序列中的多个存储器地址中预取数据的请求。 在从与第二高速缓存相关联的第二预取器接收的请求中指示该号码。 该方法的该实施例还包括从第一预取器发出在旁路存储器地址之后从存储器地址预取数据的请求。

公开(公告)号：US5386560A

公开(公告)日：1995-01-31

申请号：US704559

申请日：1991-05-23

申请人： Donald W. McCauley ,  Richard J. Schmalz ,  Ronald M. Smith, Sr. ,  Susan B. Stillman

发明人： Donald W. McCauley ,  Richard J. Schmalz ,  Ronald M. Smith, Sr. ,  Susan B. Stillman

IPC分类号： G06F13/42 ,  G06F12/02 ,  G06F13/16 ,  G06F15/17 ,  G06F13/14

CPC分类号： G06F15/17 ,  G06F13/1642

摘要： Asynchronously transfers blocks of data (called pages) between two different electronic media of a data processing system. The different media may be a system main storage and a system expanded storage or a non-volatile external type of storage, either of which use different addressing than the main storage. All of these storages may be made of DRAM or SRAM technology with battery backup when necessary. The invention splits the involvement of a program requesting a page transfer into a pair of instructions per page transfer executing on one or more central processors. The first instruction of a pair starts another processor that controls the asynchronous page transfer, and the second instruction of the pair enables the communication of the end of the page transfer to the program. Neither instruction in the pair interrupts the program for the page transfer. A processor executing the starting instruction is immediately free to execute any other available instructions. Although both instructions in a pair may be executed by one processor, the pair may be executed by separate processors. And the execution of other instructions may overlap the page transfer between the execution of the pair.

摘要翻译： 在数据处理系统的两个不同电子介质之间异步传输数据块（称为页）。 不同的媒体可以是系统主存储和系统扩展存储或非易失性外部类型的存储，其中任何一种使用与主存储不同的寻址。 所有这些存储器可以由DRAM或SRAM技术制成，并在需要时进行电池备份。 本发明将请求页面传送的程序的参与划分为在一个或多个中央处理器上执行的每页传送的一对指令。 一对的第一条指令启动另一个控制异步页面传输的处理器，该对的第二条指令使页面传送结束的通信能够与程序通信。 配对中的任一条指令都不会中断程序进行页面传送。 执行启动指令的处理器可以随时执行任何其他可用的指令。 虽然一对处理器可以执行一对指令，但该对可以由单独的处理器执行。 并且其他指令的执行可能在对的执行之间与页面传送重叠。

公开(公告)号：US4843541A

公开(公告)日：1989-06-27

申请号：US79314

申请日：1987-07-29

申请人： George H. Bean ,  Terry L. Borden ,  Mark S. Farrell ,  Peter H. Gum ,  Roger E. Hough ,  Francis E. Johnson ,  Donald W. McCauley ,  Mark E. Rakhmilevich ,  John C. Rathjen ,  Casper A. Scalzi ,  John F. Scanlon ,  Leslie W. Wyman

发明人： George H. Bean ,  Terry L. Borden ,  Mark S. Farrell ,  Peter H. Gum ,  Roger E. Hough ,  Francis E. Johnson ,  Donald W. McCauley ,  Mark E. Rakhmilevich ,  John C. Rathjen ,  Casper A. Scalzi ,  John F. Scanlon ,  Leslie W. Wyman

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F12/10

CPC分类号： G06F9/4843 ,  G06F9/5077

摘要： The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions. The guest programming systems generally will be different operating systems. The logical CPU(s) of the guests are dispatched on one or plural real CPUs in the system using the S/370XA SIE (start interpretive execution) instruction. Special operations are provided, including the CPU alerting of other guests in different partitions using I/O interruption signalling. Interception is provided to handle special circumstances.

公开(公告)号：US5615354A

公开(公告)日：1997-03-25

申请号：US471892

申请日：1995-06-07

申请人： Ronald F. Hill ,  Donald W. McCauley ,  Stephen J. Nadas ,  James R. Robinson

发明人： Ronald F. Hill ,  Donald W. McCauley ,  Stephen J. Nadas ,  James R. Robinson

IPC分类号： G06F9/312 ,  G06F9/318 ,  G06F9/355 ,  B06F9/06 ,  B06F13/10

CPC分类号： G06F9/30043 ,  G06F9/3017 ,  G06F9/342

摘要： A method and system for controlling references to system storage. Milli-code mode provides a flexible technique for overriding storage controls associated with referencing system storage of a data processing system. The storage controls to be overridden are not replaced and therefore, a restore of the previous contents of those controls is not necessary. This allows for an increase in system performance and an increase in the efficiency and flexibility of the system. In addition to the above, a system request instruction is provided, which enables flexibility in the manner in which system requests are executed. The flexibility of the system request instruction reduces the number of instructions needed to perform system requests.

摘要翻译： 一种控制系统存储引用的方法和系统。 Milli代码模式提供了一种灵活的技术，用于覆盖与引用数据处理系统的系统存储相关联的存储控制。 要覆盖的存储控制不被替换，因此，这些控件的先前内容的恢复是不必要的。 这允许系统性能的提高和系统的效率和灵活性的提高。 除了上述之外，还提供了系统请求指令，其能够以执行系统请求的方式具有灵活性。 系统请求指令的灵活性减少了执行系统请求所需的指令数量。