公开(公告)号：US06875690B2

公开(公告)日：2005-04-05

申请号：US10625027

申请日：2003-07-22

Applicant: Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

Inventor： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L21/44

CPC classification number: H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.

Abstract translation: 提供一种具有自对准接触插塞的半导体器件和制造半导体器件的方法。 半导体器件包括导电图案，第一层间绝缘层，第一间隔物，第二层间绝缘层和接触塞。 在每个导电图案中，导电层和覆盖层依次沉积在半导体衬底上的绝缘层上。 第一层间绝缘层填充导电图案之间的空间，并且具有这样的高度，使得当第一层间绝缘层放置在绝缘层上时，第一层间绝缘层低于封盖层的顶表面，但高于顶部 导电层的表面。 第一间隔件包围第一层间绝缘层上的覆盖层的外表面。 第二层间绝缘层覆盖第一层间绝缘层，覆盖层和第一间隔物，并且具有平坦化的顶表面。 接触插塞穿过第二层间绝缘层，第一层间绝缘层和导电图案之间的绝缘层电连接到半导体衬底，具有由第二间隔物包围的外壁，并且与 盖层

公开(公告)号：US20050001252A1

公开(公告)日：2005-01-06

申请号：US10858727

申请日：2004-06-02

Applicant: Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

Inventor： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

Abstract translation: 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US20080087931A1

公开(公告)日：2008-04-17

申请号：US11869400

申请日：2007-10-09

Applicant: Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L27/108 ,  H01L21/3205 ,  H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract translation: 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层， 选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

公开(公告)号：US20080085601A1

公开(公告)日：2008-04-10

申请号：US11590663

申请日：2006-10-31

Applicant: Sung-Chan Park ,  Chang-Jin Kang

Inventor： Sung-Chan Park ,  Chang-Jin Kang

IPC: B05D5/12 ,  H01L21/4763 ,  H05K3/00

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

Abstract: A method of forming a contact hole includes forming a plurality of lower patterns on a substrate. An insulation layer is formed on the lower patterns. A self-assemble induction layer is formed on the insulation layer. A recess is formed in the self-assemble induction layer in alignment with the lower patterns. A block copolymer layer is formed in the recess to form a polymer domain at a distance from a sidewall of the recess and a polymer matrix surrounding the polymer domain. The polymer domain is removed. The self-assemble induction layer is etched using the polymer matrix as a mask to form an opening through the self-assemble induction layer to expose the insulation layer. The insulation layer exposed by the opening is etched using the self-assemble induction layer as a mask so as to form a contact hole.

Abstract translation: 形成接触孔的方法包括在基板上形成多个下部图案。 在下部图案上形成绝缘层。 在绝缘层上形成自组装感应层。 在自组装感应层中形成与下部图形对准的凹部。 在凹部中形成嵌段共聚物层，以形成与凹陷的侧壁相距一定距离的聚合物结构域和围绕聚合物结构域的聚合物基体。 去除聚合物结构域。 使用聚合物基质作为掩模蚀刻自组装感应层，以通过自组装感应层形成开口以暴露绝缘层。 使用自组装感应层作为掩模蚀刻由开口暴露的绝缘层，以形成接触孔。

公开(公告)号：US20080081432A1

公开(公告)日：2008-04-03

申请号：US11624905

申请日：2007-01-19

Applicant: Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

Inventor： Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC: H01L21/76

CPC classification number: H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner wails of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

Abstract translation: 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US20050275042A1

公开(公告)日：2005-12-15

申请号：US11138034

申请日：2005-05-26

Applicant: Sung-Wook Hwang ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

Inventor： Sung-Wook Hwang ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/74

CPC classification number: H01L29/4236 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/66621

Abstract: A semiconductor device including a transistor and a method of forming thereof are provided. The semiconductor device comprises a metal gate electrode. A lower portion of the metal gate electrode fills a channel trench formed at a predetermined region of a substrate, and an upper portion of the metal gate electrode protrudes on the substrate. A gate insulating layer is interposed between inner sidewalls and a bottom surface of the channel trench, and the metal gate electrode. Source/drain regions are formed at the substrate in both sides of the metal gate electrode.

Abstract translation: 提供了包括晶体管及其形成方法的半导体器件。 半导体器件包括金属栅电极。 金属栅电极的下部填充形成在衬底的预定区域处的沟道沟槽，并且金属栅电极的上部在衬底上突出。 栅极绝缘层插入在沟道沟槽的内侧壁和底表面之间以及金属栅电极之间。 源极/漏极区域形成在金属栅电极两侧的衬底处。

公开(公告)号：US20050003310A1

公开(公告)日：2005-01-06

申请号：US10802150

申请日：2004-03-17

Applicant: Keun-Hee Bai ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Myeong-Cheol Kim

Inventor： Keun-Hee Bai ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Myeong-Cheol Kim

IPC: H01L21/3065 ,  G03F7/36 ,  G03F7/40 ,  H01L21/027 ,  H01L21/311

CPC classification number: G03F7/40 ,  H01L21/0276 ,  H01L21/31144

Abstract: An etching process including plasma pretreatment for generating a polymer layer formed of carbon on a photoresist pattern. The photoresist pattern is treated with plasma that does not contain fluorine radicals and that provides carbon radicals. An etching process is performed on an etching target layer by using the photoresist pattern as an etch mask.

Abstract translation: 一种蚀刻工艺，包括用于在光致抗蚀剂图案上产生由碳形成的聚合物层的等离子体预处理。 用不含氟自由基并提供碳自由基的等离子体处理光致抗蚀剂图案。 通过使用光致抗蚀剂图案作为蚀刻掩模，在蚀刻目标层上进行蚀刻处理。

公开(公告)号：US06753221B2

公开(公告)日：2004-06-22

申请号：US10322274

申请日：2002-12-17

Applicant: Jeong-Sic Jeon ,  Chang-Jin Kang ,  Seung-Young Son ,  Jin-Hong Kim

Inventor： Jeong-Sic Jeon ,  Chang-Jin Kang ,  Seung-Young Son ,  Jin-Hong Kim

IPC: H01L218242

CPC classification number: H01L27/10852 ,  H01L21/31116 ,  H01L21/32136 ,  H01L27/10894 ,  H01L28/55 ,  H01L28/91

Abstract: Methods for fabricating semiconductor devices having capacitors are provided. A plurality of storage node electrodes are formed on a semiconductor substrate. Then, a capacitor dielectric layer is formed over the storage node electrodes. A plate electrode layer is subsequently formed on the capacitor dielectric layer. A hard mask layer is then formed on the resultant structure where the plate electrode layer is formed so as to fill a gap between the adjacent storage node electrodes. The hard mask layer and the plate electrode layer are successively patterned to form a plate electrode.

Abstract translation: 提供了制造具有电容器的半导体器件的方法。 多个存储节点电极形成在半导体衬底上。 然后，在存储节点电极上形成电容器电介质层。 随后在电容器电介质层上形成平板电极层。 然后在其上形成平板电极层的所得结构上形成硬掩模层，以填充相邻存储节点电极之间的间隙。 硬掩模层和平板电极层依次构图以形成平板电极。

公开(公告)号：US07618899B2

公开(公告)日：2009-11-17

申请号：US11847223

申请日：2007-08-29

Applicant: Seung-Pil Chung ,  Dong-Chan Kim ,  Chang-Jin Kang ,  Heung-Sik Park

Inventor： Seung-Pil Chung ,  Dong-Chan Kim ,  Chang-Jin Kang ,  Heung-Sik Park

IPC: H01L21/31 ,  H01L21/308

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086

Abstract: Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer in a first direction, coating a high molecular organic material layer on the line sacrificial hard mask layer pattern, patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in a second direction, forming a matrix sacrificial hard mask layer pattern, forming a hard mask layer pattern by patterning the hard mask layer with the matrix sacrificial hard mask layer pattern as an etching mask and forming a lower pattern by patterning the base layer using the hard mask layer pattern as an etch mask. The method according to the invention is simpler and less expensive than conventional methods.

Abstract translation: 公开了制造半导体集成电路器件的方法。 制造半导体集成电路器件的方法包括在基底层上形成硬掩模层，在第一方向上在硬掩模层上形成线牺牲硬掩模层，在牺牲硬掩模上涂覆高分子有机材料层 层状图案，在第二方向上图案化高分子有机材料层和线牺牲硬掩模层图案，形成矩阵牺牲硬掩模层图案，通过用基体牺牲硬掩模图案化硬掩模层形成硬掩模层图案 层图案作为蚀刻掩模，并且通过使用硬掩模层图案作为蚀刻掩模对基底层进行图案化来形成下图案。 根据本发明的方法比常规方法更简单和便宜。

公开(公告)号：US07491344B2

公开(公告)日：2009-02-17

申请号：US10703947

申请日：2003-11-04

Applicant: Heung-Sik Park ,  Chang-Jin Kang ,  Tae-Hyuk Ahn ,  Kyeong-Koo Chi ,  Sang-Hun Seo

Inventor： Heung-Sik Park ,  Chang-Jin Kang ,  Tae-Hyuk Ahn ,  Kyeong-Koo Chi ,  Sang-Hun Seo

IPC: C23F1/00

CPC classification number: H01J37/32055 ,  H01L21/3065 ,  H01L21/78 ,  H05H1/44

Abstract: Disclosed herein is a method for etching a face of an object and more particularly a method for etching a rear face of a silicon substrate. The object having a silicon face is positioned so as to be spaced apart from a plasma-generating member by a predetermined interval distance. The plasma-generating member generates arc plasmas to form a plasma region. A reaction gas is allowed to pass through the plasma region to generate radicals having high energies and high densities. The radicals react with the object to etch the face of the object. The face of the object can be rapidly and uniformly etched.

Abstract translation: 本文公开了一种用于蚀刻物体的表面的方法，更具体地，蚀刻硅衬底的背面的方法。 具有硅面的物体被定位成与等离子体产生构件间隔预定间隔距离。 等离子体产生部件产生电弧等离子体以形成等离子体区域。 允许反应气体通过等离子体区域以产生具有高能量和高密度的自由基。 自由基与物体反应以蚀刻物体的表面。 物体的表面可以快速均匀地蚀刻。