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公开(公告)号：US09800261B2
公开(公告)日：2017-10-24
申请号：US15405628
申请日：2017-01-13
Inventor： Young Kyun Cho , Bong Hyuk Park
CPC classification number: H03M3/454 , H03H11/1204 , H03H11/1291 , H03M3/422 , H03M3/43 , H03M3/452 , H03M3/464
Abstract: A third-order loop filter for a delta signal modulator comprises a single operational amplifier, and a resistor-capacitor network including a plurality of capacitors and a plurality of resistors which are connected to the operational amplifier, and satisfy a third-order transfer function.
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公开(公告)号：US09755321B2
公开(公告)日：2017-09-05
申请号：US15006283
申请日：2016-01-26
Inventor： Young Kyun Cho , Bong Hyuk Park , Jung Hoon Oh , Jung Nam Lee , Gweon Do Jo
Abstract: A smart antenna system according to an exemplary embodiment of the present invention including a beam forming antenna which includes an active antenna and a plurality of parasitic antennas, the system including: a reactance load which is connected to the parasitic antenna; a transceiver which transmits and receives a signal to the beam forming antenna; and an antenna adjusting block which tracks a signal source in real time using a plurality of beam patterns having the largest signal size and forms a beam in a direction having the largest signal size.
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13.发明授权Second order loop filter and multi-order delta sigma modulator including the same 有权二阶环路滤波器和包括其的多阶三角Σ调制器公开(公告)号：US09356618B2
公开(公告)日：2016-05-31
申请号：US14617705
申请日：2015-02-09
Inventor： Young Kyun Cho , Jae Ho Jung , Kwangchun Lee
CPC classification number: H03M3/43 , H03H11/1247 , H03H11/126 , H03H11/1291 , H03H11/32 , H03M3/38 , H03M3/422 , H03M3/454 , H03M3/458
Abstract: Provided is a second order loop filter (LF). The second order LF includes: an operational amplifier including a first input, a second input receiving a differential input of the first input, and an output; an inverter inverting a signal output from the output of the operational amplifier to output an inverted signal; a first resistor connected to between the first input and a first node; a second resistor connected to between the output of the operational amplifier and the first node; a third resistor connected to between the first input and an input signal; a first capacitor connected to between the second input and the first node; a second capacitor connected to between the output of the operational amplifier and an output of the inverter; and a third capacitor connected to between the output and the first input of the operational amplifier, wherein the second input is connected to a ground voltage.
Abstract translation: 提供了二阶环路滤波器（LF）。 第二级LF包括：运算放大器，包括第一输入端，接收第一输入端的差分输入端的第二输入端和输出端; 逆变器，反相从运算放大器的输出端输出的信号，输出反相信号; 连接到第一输入和第一节点之间的第一电阻器; 连接到运算放大器的输出端和第一节点之间的第二电阻器; 连接到所述第一输入端和输入信号之间的第三电阻器; 连接到所述第二输入端和所述第一节点之间的第一电容器; 连接在运算放大器的输出端和反相器的输出端之间的第二电容器; 以及连接到所述运算放大器的输出和第一输入之间的第三电容器，其中所述第二输入端连接到接地电压。
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14.发明授权Apparatus and method for calibrating offset voltage and continuous time delta-sigma modulation apparatus including the same 有权用于校正偏移电压的装置和方法以及包括其的连续时间Δ-Σ调制装置公开(公告)号：US08791846B2
公开(公告)日：2014-07-29
申请号：US13707135
申请日：2012-12-06
Inventor： Young Kyun Cho , Jae Ho Jung , Kwangchu Lee
IPC: H03M3/00
Abstract: When an enable signal representing an offset calibration mode is received, a continuous time delta-sigma modulation apparatus generates a first signal using first and second pulse signals representing outputs of the continuous time delta-sigma modulation apparatus and an operation frequency of the continuous time delta-sigma modulation apparatus, generates first and second output bits by performing a counting operation according to a counting method that is determined according to a pulse signal of first and second comparators, applies a voltage corresponding to the first output bit to a body of a first transistor of a primary integrator, and applies a voltage corresponding to the second output bit to a body of a second transistor of the primary integrator.
Abstract translation: 当接收到表示偏移校准模式的使能信号时，连续时间Δ-Σ调制装置使用表示连续时间Δ-Σ调制装置的输出的第一和第二脉冲信号和连续时间delta的操作频率来产生第一信号 Σ调制装置通过根据根据第一和第二比较器的脉冲信号确定的计数方法执行计数操作来产生第一和第二输出比特，将与第一输出比特相对应的电压施加到第一 晶体管，并且将与第二输出位相对应的电压施加到主积分器的第二晶体管的主体。
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公开(公告)号：US11290014B2
公开(公告)日：2022-03-29
申请号：US16939567
申请日：2020-07-27
Inventor： Young Kyun Cho , Tae Joong Kim , Kwang Chun Lee , Jung Nam Lee , Jae Ho Jung
Abstract: A boost direct current-to-direct current (DC-DC) converter using a delta-sigma modulator (DSM), the boost DC-DC converter may comprise a boost driving circuit outputting an output voltage to output terminals by boosting an input voltage, a resistance distribution circuit outputting a feedback voltage by distributing the output voltage of the boost driving circuit, a compensator outputting a compensated feedback voltage by compensating for the feedback voltage outputted by the resistance distribution circuit based on a reference voltage, a delta-sigma modulator outputting a digital signal by modulating the compensated feedback voltage and a duty controller outputting a duty control signal for controlling a switching duty of the boost driving circuit by receiving the output of the delta-sigma modulator.
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Patent Agency Ranking
公开(公告)号：US09479120B2
公开(公告)日：2016-10-25
申请号：US14612801
申请日：2015-02-03
Inventor： Young Kyun Cho , Jae Ho Jung , Kwangchun Lee
CPC classification number: H03F1/083 , H03F3/45475 , H03F3/45941 , H03F2200/129 , H03F2200/153 , H03F2203/45114 , H03F2203/45424 , H03F2203/45521
Abstract: Provided is a fully differential signal system including a first amplification unit including first and second output terminals configured to output an output differential signal generated based on an input differential signal and a common mode feedback signal; a common mode detection unit configured to detect a common mode signal included in the output differential signal; a second amplification unit including a feedback signal output terminal configured to output the common mode feedback signal generated based on the detected common mode signal and a reference signal; a first stabilization unit connected between the first output terminal and the feedback signal output terminal; and a second stabilization unit connected between the second output terminal and the feedback signal output terminal. The fully differential signal system stably operates and an operation performance of the fully differential signal system is improved.
Abstract translation: 提供了一种全差分信号系统，包括：第一放大单元，包括第一和第二输出端子，第一和第二输出端子被配置为输出基于输入差分信号和共模反馈信号产生的输出差分信号; 共模检测单元，被配置为检测包括在所述输出差分信号中的共模信号; 第二放大单元，包括反馈信号输出端子，其被配置为输出基于检测到的共模信号产生的共模反馈信号和参考信号; 连接在第一输出端子和反馈信号输出端子之间的第一稳定单元; 以及连接在第二输出端子和反馈信号输出端子之间的第二稳定单元。 全差分信号系统稳定运行，提高了全差分信号系统的运行性能。
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17.发明授权公开(公告)号：US09300513B2
公开(公告)日：2016-03-29
申请号：US14595653
申请日：2015-01-13
Inventor： Seunghyun Jang , Young Kyun Cho , Sung Jun Lee , Bong Hyuk Park , Jae Ho Jung , Kwangchun Lee
CPC classification number: H04L27/2627 , H03F1/3247 , H03F3/24 , H04L25/4902 , H04L25/4923 , H04L27/20 , H04L27/368
Abstract: Provided is a signal transmission device including a first modulation unit generating a first modulated signal having at least three logic levels by modulating an input signal; a characteristic adjustment unit generating an adjusted first modulated signal by adjusting the at least one of electrical characteristic values based on an adjustment signal; a second modulation unit generating a second modulated signal by modulating the adjusted first modulated signal; and an adjustment operation unit generating the adjustment signal based on electrical characteristic values respectively corresponding to the at least three logic levels of the first modulated signal and corresponding to at least three logic levels of the second modulated signal. Linearity of the modulated signal generated by the provided signal transmission device is enhanced.
Abstract translation: 提供了一种信号传输设备，包括：第一调制单元，通过调制输入信号产生具有至少三个逻辑电平的第一调制信号; 特征调整单元，通过基于调整信号调整所述电特性值中的至少一个来生成经调整的第一调制信号; 第二调制单元，通过调制经调整的第一调制信号产生第二调制信号; 以及调整操作单元，其基于分别对应于所述第一调制信号的所述至少三个逻辑电平并对应于所述第二调制信号的至少三个逻辑电平的电特性值生成所述调整信号。 由提供的信号传输装置产生的调制信号的线性增强。
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公开(公告)号：US09295001B2
公开(公告)日：2016-03-22
申请号：US14150084
申请日：2014-01-08
Inventor： Seunghyun Jang , Sung Jun Lee , Young Kyun Cho , Bong Hyuk Park , Jae Ho Jung , Kwangchun Lee
CPC classification number: H04W52/04 , H04W52/241 , H04W52/52
Abstract: A signal amplification apparatus includes a first modulator configured to receive an envelope signal, use a predetermined reference level to separate the received envelope signal into a first period and a second period, digitally modulate a signal of the second period to output the digitally modulated signal to a first output terminal, and output a signal of the first period to a second output terminal. Further, the signal amplification apparatus includes a second modulator configured to mix the digital modulated signal input through the first output terminal with a phase modulated carrier signal; an envelope modulator configured to output the signal of the first period as a power supply signal; and a power amplifier configured to amplify the mixed signal output by the second modulator to output the amplified signal.
Abstract translation: 信号放大装置包括：第一调制器，被配置为接收包络信号，使用预定的参考电平将接收的包络信号分离成第一周期和第二周期，数字地调制第二周期的信号以输出数字调制信号 第一输出端，并将第一周期的信号输出到第二输出端。 此外，信号放大装置包括：第二调制器，被配置为将通过第一输出端子输入的数字调制信号与相位调制载波信号混合; 包络调制器，被配置为输出所述第一周期的信号作为电源信号; 以及功率放大器，被配置为放大由第二调制器输出的混合信号以输出放大的信号。
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19.发明授权公开(公告)号：US09143310B2
公开(公告)日：2015-09-22
申请号：US14294836
申请日：2014-06-03
Inventor： Sung Jun Lee , Young Kyun Cho , Seunghyun Jang , Bong Hyuk Park , Jae Ho Jung , Kwangchun Lee
CPC classification number: H04L7/0016 , H04L27/366 , H04L27/02 , H04L27/361
Abstract: Provided is a method of correcting a time misalignment between envelope and phase components in a transmitting apparatus which separates envelope and phase components of a signal, processes them, and then recombines them to transmit the recombined signal. For this, in a method of correcting a time misalignment between envelope and phase components according to an embodiment of the present invention, a time misalignment is corrected by applying a time delay to at least one of envelope and phase components in digital and analog signal processing operations, or applying a time delay to an envelope or phase component by a pre-processing operation.
Abstract translation: 提供了一种校正发送装置中的包络和相位分量之间的时间偏移的方法，该发送装置分离信号的包络和相位分量，处理它们，然后将它们复合以发送重组信号。 为此，在根据本发明的实施例的校正包络和相位分量之间的时间失准的方法中，通过对数字和模拟信号处理中的包络和相位分量中的至少一个应用时间延迟来校正时间偏移 操作或通过预处理操作对信封或相位分量施加时间延迟。
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公开(公告)号：US09143145B2
公开(公告)日：2015-09-22
申请号：US14308752
申请日：2014-06-19
Inventor： Young Kyun Cho , Jae Ho Jung , Kwangchun Lee
Abstract: Provided is a delta-sigma modulator including a summer summing an input signal and an analog signal, a first integrator integrating an output signal from the summer and outputting a first integration signal, a second integrator integrating the first integration signal and outputting a second integration signal, a comparator comparing the second integration signal and a reference signal and outputting a digital signal according to the comparison result, and a digital-to-analog converter converting the digital signal into an analog signal in response to a clock signal and outputting the converted analog signal, wherein the second integrator operates based on an Nth order (where N is natural number of 1 or greater) transfer function.
Abstract translation: 提供了一种Δ-Σ调制器，其包括对输入信号和模拟信号进行加法求和，第一积分器，对来自加法器的输出信号进行积分并输出第一积分信号;第二积分器，积分第一积分信号并输出第二积分信号 比较比较第二积分信号和参考信号的比较器，并根据比较结果输出数字信号;以及数模转换器，响应于时钟信号将数字信号转换为模拟信号，并输出转换的模拟 信号，其中所述第二积分器基于N阶（其中N是1或更大的自然数）传递函数来操作。
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