公开(公告)号：US06236617B1

公开(公告)日：2001-05-22

申请号：US09458878

申请日：1999-12-10

Applicant: Louis L. Hsu ,  Hans-Oliver Joachim ,  Matthew R. Wordeman ,  Hing Wong

Inventor： Louis L. Hsu ,  Hans-Oliver Joachim ,  Matthew R. Wordeman ,  Hing Wong

IPC: G11C800

CPC classification number: G11C8/08

Abstract: A negative wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted wordline high voltage (2.8 v) greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted wordline high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 &mgr;A) because Vqs on the nfet is nearly at the nfet threshold. The net active power from the entire array is less than that of a conventional configuration due to the reduced voltage swing, while the number of transistors exposed to high voltage stress is reduced from 9 to 1 and the number of buffer nfets required to reduce voltage drop across an active nfet is reduced from 8 to 1.

Abstract translation: 具有n组m个字线的负字形DRAM阵列暴露于一组，其中一组由组解码器电路（具有地面之间的电压摆幅和电路高电压（2v））和每组中的一个驱动器电路驱动 提升的字线高电压（2.8V）大于电路高电压，其中字线驱动器电路具有包括与高阈值电压pfet串联的标准nfet的输出级，使得在激活期间，未选择的驱动器电路暴露 对于升压的字线高电压通过pfet具有非常低的泄漏，而所选择的驱动器电路具有高但可容许的泄漏（2μA），因为nfet上的Vqs几乎处于nfet阈值。 由于降低的电压摆幅，整个阵列的净有功功率小于传统配置的功率，而暴露于高电压应力的晶体管的数量从9减少到1，并且减少电压降所需的缓冲器数量 跨越一个活跃的nfet从8减少到1。

公开(公告)号：US5848008A

公开(公告)日：1998-12-08

申请号：US937528

申请日：1997-09-25

Applicant: Toshiaki Kirihata ,  Hing Wong ,  Bozidar Krsnik

Inventor： Toshiaki Kirihata ,  Hing Wong ,  Bozidar Krsnik

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/04 ,  G11C29/50 ,  G11C29/56 ,  G11C7/00

CPC classification number: G11C29/50

Abstract: A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.

Abstract translation: 提供一种使用数字可控位线均衡器产生浮动位线测试模式的方法。 该方法利用数字控制的虚拟定时周期来检测浮动位线测试模式期间的泄漏位线。 产生负脉冲+ E，ovs TEST + EE信号，使位线均衡器变为低电平，并导致浮置位线状态。 虚拟定时周期的实现消除了在位线测试模式期间对内部定时的额外外部控制的需要。 在虚拟定时周期结束时，正常读取操作继续而不中断。

公开(公告)号：US5741738A

公开(公告)日：1998-04-21

申请号：US604283

申请日：1996-02-21

Applicant: Jack A. Mandelman ,  Brian J. Machesney ,  Hing Wong ,  Michael M. Armacost ,  Pai-Hung Pan

Inventor： Jack A. Mandelman ,  Brian J. Machesney ,  Hing Wong ,  Michael M. Armacost ,  Pai-Hung Pan

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.

Abstract translation: 一种用于防止栅包绕和角寄生泄漏的半导体结构，包括具有平坦表面的半导体衬底。 沟槽位于衬底中，沟槽具有侧壁。 沟槽和表面的交点形成一个角落。 介电线路沟槽的侧壁。 并且，与拐角共同对准的拐角电介质在拐角处延伸超过衬底的最小尺寸距离。

公开(公告)号：US5615164A

公开(公告)日：1997-03-25

申请号：US477063

申请日：1995-06-07

Applicant: Toshiaki Kirihata ,  Hing Wong

Inventor： Toshiaki Kirihata ,  Hing Wong

IPC: G11C11/413 ,  G11C8/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/02 ,  G11C29/06 ,  G11C29/12 ,  G11C29/34 ,  G11C29/50 ,  G11C8/00

CPC classification number: G11C29/025 ,  G11C29/02 ,  G11C29/34 ,  G11C29/50 ,  G11C8/10 ,  G11C11/401

Abstract: A latched row decoder for a Random Access Memory (RAM). The Decoder includes a set-reset latch that is set when addressed and remains set until reset by a PRE signal; address select logic; a reset device; and gated word line drives. The latch, when set, enables four word line drivers that are driven individually depending on two row address bits. During test, latched decoders may be selected sequentially and not reset, leaving drivers enabled until a test is complete. Thus some or all word lines may be driven simultaneously during test. A RAM including the latched decoder of the present invention has a normal random access mode and at least 4 test modes. The test modes are: Long t.sub.RAS word line disturb mode; toggled word line disturb mode; transfer gate stress mode; and a stress test mode.

Abstract translation: 用于随机存取存储器（RAM）的锁存行解码器。 解码器包括设置复位锁存器，其在寻址时被置位并保持置位，直到由PRE信号复位; 地址选择逻辑; 复位装置; 和门控驱动器。 当锁存器置位时，可以根据两个行地址位单独驱动四个字线驱动器。 在测试期间，锁存解码器可以顺序选择并且不复位，使驱动器启用，直到测试完成。 因此，在测试期间可以同时驱动一些或所有字线。 包括本发明的锁存解码器的RAM具有正常的随机存取模式和至少4个测试模式。 测试模式为：长tRAS字线干扰模式; 切换字线干扰模式; 传输门应力模式; 和压力测试模式。

公开(公告)号：US5517442A

公开(公告)日：1996-05-14

申请号：US402790

申请日：1995-03-13

Applicant: Toshiaki Kirihata ,  Yohji Watanabe ,  Hing Wong

Inventor： Toshiaki Kirihata ,  Yohji Watanabe ,  Hing Wong

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C29/00 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C29/80 ,  G11C7/10

Abstract: The present invention is a bus arrangement for a wide I/O Random Access Memory (RAM). The bus arrangement includes a global address bus which drives row/column predecoders and redundancy comparators placed at each edge of the memory array. Two banks of sixteen data I/O (DQs), one bank for each half chip, are placed at either end of the chip providing up to a .times.32 I/O organization. The main Read/Write Data lines (RWD) are more densely populated near the chip edge than the chip center to provide .times.4 and .times.8 options, as well. A local address bus is in the open space between the RWDs to redrive the global address lines at their quarter points.

Abstract translation: 本发明是用于宽I / O随机存取存储器（RAM）的总线装置。 总线布置包括全局地址总线，其驱动行/列预解码器和放置在存储器阵列的每个边缘处的冗余比较器。 十六个数据I / O（DQ）的两组，每个半芯片的一个存储区，放置在芯片的任一端，提供一个x32 I / O组织。 主芯片读/写数据线（RWD）在芯片边缘附近比芯片中心更密集，以提供x4和x8选项。 本地地址总线位于RWD之间的开放空间，以便在其四分之一点重新启动全局地址线。

公开(公告)号：US08372958B2

公开(公告)日：2013-02-12

申请号：US10601171

申请日：2003-06-23

Applicant: Gerald W. Fischer ,  Richard F. Schuman ,  Hing Wong ,  Jeffrey R. Stinson

Inventor： Gerald W. Fischer ,  Richard F. Schuman ,  Hing Wong ,  Jeffrey R. Stinson

IPC: C07K16/00 ,  C12P21/08

CPC classification number: C07K14/195 ,  A61K38/00 ,  A61K39/00 ,  A61K2039/505 ,  C07K16/1267 ,  C07K16/1271 ,  C07K2317/24 ,  C07K2317/33 ,  C07K2317/34 ,  C07K2317/73 ,  C07K2317/77 ,  C07K2319/00

Abstract: The present invention encompasses monoclonal and chimeric antibodies that bind to lipoteichoic acid of Gram positive bacteria. The antibodies also bind to whole bacteria and enhance phagocytosis and killing of the bacteria in vitro and enhance protection from lethal infection in vivo. The mouse monoclonal antibody has been humanized and the resulting chimeric antibody provides a previously unknown means to diagnose, prevent and/or treat infections caused by gram positive bacteria bearing lipoteichoic acid. This invention also encompasses a peptide mimic of the lipoteichoic acid epitope binding site defined by the monoclonal antibody. This epitope or epitope peptide mimic identifies other antibodies that may bind to the lipoteichoic acid epitope. Moreover, the epitope or epitope peptide mimic provides a valuable substrate for the generation of vaccines or other therapeutics.

Abstract translation: 本发明包括与革兰氏阳性细菌的脂磷壁酸结合的单克隆抗体和嵌合抗体。 抗体还结合全细菌，增强体外吞噬细菌和杀死细菌，增强体内致死感染的保护作用。 小鼠单克隆抗体已经人源化，所得到的嵌合抗体提供了以前未知的用于诊断，预防和/或治疗由具有脂磷壁酸的革兰氏阳性细菌引起的感染的方法。 本发明还包括由单克隆抗体限定的脂磷壁酸结合位点的肽模拟物。 该表位或表位肽模拟物鉴定可结合脂磷壁酸表位的其它抗体。 此外，表位或表位肽模拟物为生成疫苗或其他治疗剂提供了有价值的底物。

公开(公告)号：US20070003560A1

公开(公告)日：2007-01-04

申请号：US11471369

申请日：2006-06-20

Applicant: Jeffrey Stinson ,  Hing Wong ,  Alison O'Brien ,  Clare Schmitt ,  Angela Melton-Celsa

Inventor： Jeffrey Stinson ,  Hing Wong ,  Alison O'Brien ,  Clare Schmitt ,  Angela Melton-Celsa

IPC: A61K39/40 ,  C07H21/04 ,  C12P21/06 ,  C12N5/06 ,  C07K16/12

CPC classification number: C07K16/1232 ,  A61K38/00 ,  C07K2317/24 ,  C07K2319/00

Abstract: The present invention describes the preparation and use of biologically and immunologically active humanized monoclonal antibodies to Shiga toxin, a toxin associated with HC and the potentially life-threatening sequela HUS transmitted by strains of pathogenic bacteria. The present invention describes how these humanized antibodies may be used in the treatment or prevention of Shiga toxin induced diseases. One aspect of the invention is the humanized monoclonal antibody which binds Shiga toxin where the constant regions are IgG1-kappa and the variable regions are murine in origin. Yet another aspect of the invention is expression vectors and host cells transformed with such vectors which express the humanized monoclonal antibodies of the present invention.

Abstract translation: 本发明描述了生物学和免疫学活性的人源化单克隆抗体与志贺毒素（一种与HC相关的毒素）和潜在的危及生命的后遗症HUS由病原菌菌株传播的制备和应用。 本发明描述了这些人源化抗体如何用于治疗或预防志贺毒素诱导的疾病。 本发明的一个方面是结合志贺毒素的人源化单克隆抗体，其中恒定区是IgG1-κ，可变区是起源的鼠。 本发明的另一方面是用表达本发明的人源化单克隆抗体的载体转化的表达载体和宿主细胞。

公开(公告)号：US20050089929A1

公开(公告)日：2005-04-28

申请号：US10618338

申请日：2003-07-11

Applicant: Jin-an Jiao ,  Hing Wong ,  Jinghai Wen

Inventor： Jin-an Jiao ,  Hing Wong ,  Jinghai Wen

IPC: A61K38/00 ,  A61K39/395 ,  C07K16/28 ,  C07K16/36 ,  G01N33/53 ,  C07K16/22

CPC classification number: A61K39/395 ,  A61K38/00 ,  C07K16/36 ,  A61K2300/00

Abstract: Disclosed are antibodies that provide superior anti-coagulant activity by binding native human TF with high affinity and specificity. Also disclosed are methods of using such antibodies to reduce cancer cell tissue factor activity and to detect cancer cells that express TF.

Abstract translation: 公开了通过以高亲和力和特异性结合天然人TF提供优异的抗凝血活性的抗体。 还公开了使用这种抗体降低癌细胞组织因子活性并检测表达TF的癌细胞的方法。

公开(公告)号：US06288922B1

公开(公告)日：2001-09-11

申请号：US09637124

申请日：2000-08-11

Applicant: Hing Wong ,  Subramani Kengeri

Inventor： Hing Wong ,  Subramani Kengeri

IPC: G11C1500

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: The invention discloses a low-power ternary CAM by utilizing four encoded comparand datalines, C0, C1, C2, and C3 in a twin ternary cell. The twin ternary cell is a composite of two ternary CAM bits. The two binary CAM bits are coded so that only one of four comparand datalines is toggled during a compare operation. The encoded data is stored and used for comparison. In one embodiment, the four possible states for the 2 bit comparands are coded as 0001, 0010, 0100, and 1000.

Abstract translation: 本发明公开了一种低功率三元CAM，通过在双三进制单元中利用四个编码的比较数据，C0，C1，C2和C3。 双胞胎单元是两个三进制CAM位的组合。 两个二进制CAM位被编码，使得在比较操作期间只切换四个比较数据的一个。 编码数据被存储并用于比较。 在一个实施例中，用于2比较比较的四种可能状态被编码为0001，0010，0100和1000。

公开(公告)号：US6115300A

公开(公告)日：2000-09-05

申请号：US186215

申请日：1998-11-03

Applicant: Ali Massoumi ,  Hing Wong

Inventor： Ali Massoumi ,  Hing Wong

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/846

Abstract: DRAM with column slices improves circuit redundancy. Slices have global column length, and memory is divided in groups with size of redundancy columns having slices. Failure detected among slices of corresponding storage is replaced by corresponding redundancy column slice, such that column redundancy division is in vertical column direction. Column includes global data line shared by column slices and multiple blocks. Redundant column is added to memory array, and redundant control circuits or comparator are proximate to data sense amplifiers. Defective column address are provided to controller through non-volatile memory, or laser-blown or electrically-programmable fuses. When column address is presented, incoming address is compared with stored address, such that select data is output on redundant data line when equal addresses (i.e., hit detect), or normal data is output when unequal addresses (i.e., "miss" detected).

Abstract translation: 具有列切片的DRAM提高了电路冗余性。 切片具有全局列长度，并且存储器被划分成具有切片大小的冗余列的组。 在相应的存储器片中检测到的故障由相应的冗余列片段替代，使得列冗余分割处于垂直列方向。 列包括由列切片和多个块共享的全局数据行。 冗余列被添加到存储器阵列中，并且冗余控制电路或比较器靠近数据读出放大器。 通过非易失性存储器或激光熔断或电可编程保险丝将故障列地址提供给控制器。 当列地址被显示时，输入地址与存储的地址进行比较，使得当相等地址（即，命中检测）或在不等地址（即“未检测到”地址时）输出正常数据时，在冗余数据线上输出选择数据， 。