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公开(公告)号：US08248884B2
公开(公告)日：2012-08-21
申请号：US12975322
申请日：2010-12-21
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device includes a clock receiver, a command interface, and a data interface separate from the command interface. A memory controller provides the command interface with a command that specifies a write operation. After a programmable latency period transpires from providing the command, data associated with the write operation is provided to the data interface by the memory controller. The memory controller provides power mode information that controls transitions between a plurality of power modes, where for each power mode of the plurality of power modes, less power is consumed than the amount of power consumed during the write operation. The power modes include a mode in which the clock receiver is on and the data interface is off; and a mode in which the clock receiver is off and the data interface is off.
摘要翻译： 存储器件包括时钟接收器，命令接口和与命令接口分开的数据接口。 存储器控制器为命令接口提供指定写入操作的命令。 在从提供命令开始可编程的等待时间之后，由写入操作相关联的数据由存储器控制器提供给数据接口。 存储器控制器提供功率模式信息，其控制多个功率模式之间的转换，其中对于多个功率模式的每个功率模式，消耗的功率比在写入操作期间消耗的功率量少。 功率模式包括时钟接收器接通和数据接口关闭的模式; 以及时钟接收器关闭且数据接口关闭的模式。
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公开(公告)号：US07986584B2
公开(公告)日：2011-07-26
申请号：US12608209
申请日：2009-10-29
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
摘要翻译： 描述了具有存储器核心的存储器件。 存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。 数据接口与第一个接口分开。 第二个接口与第一个接口和数据接口分开。 存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。 在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。
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公开(公告)号：US06708248B1
公开(公告)日：2004-03-16
申请号：US09457155
申请日：1999-12-08
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G06F1200
CPC分类号： G06F13/1657 , G06F13/1684 , Y02D10/14
摘要： A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.
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公开(公告)号：US06356975B1
公开(公告)日：2002-03-12
申请号：US09169526
申请日：1998-10-09
申请人： Richard M. Barth , Ely K. Tsern , Mark A. Horowitz , Donald C. Stark , Craig E. Hampel , Frederick A. Ware , John B. Dillon , by Nancy David Dillon
发明人： Richard M. Barth , Ely K. Tsern , Mark A. Horowitz , Donald C. Stark , Craig E. Hampel , Frederick A. Ware , John B. Dillon , by Nancy David Dillon
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.
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公开(公告)号：US20120057424A1
公开(公告)日：2012-03-08
申请号：US13253911
申请日：2011-10-05
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
摘要翻译： 描述了具有存储器核心的存储器件。 存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。 数据接口与第一个接口分开。 第二个接口与第一个接口和数据接口分开。 存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。 在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。
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公开(公告)号：US07626880B2
公开(公告)日：2009-12-01
申请号：US11107504
申请日：2005-04-15
IPC分类号： G11C11/06
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.
摘要翻译： 描述了具有存储器核心的存储器件。 存储器件包括时钟接收器电路，控制接口，数据接口，延迟锁定环电路，读取流水线电路和用于提供内部时钟信号的电路。 时钟接收器电路接收外部时钟信号。 控制接口接收指定对存储器件的读取操作的命令。 数据接口在存储器件和外部信号线组之间传送数据。 延迟锁定环路电路，耦合到时钟接收器电路，以使用外部时钟信号产生内部时钟信号。 读取管线电路将从存储器核心访问的读取数据提供给数据接口。 响应于接收到指定读取操作的命令，该电路将内部时钟信号提供给读取管线电路。
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公开(公告)号：US07320082B2
公开(公告)日：2008-01-15
申请号：US10742327
申请日：2003-12-18
IPC分类号： G06F1/00
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.
摘要翻译： 具有多个时钟域的存储器件。 将时钟分离到控制电路的不同部分，创建不同的时钟域。 根据需要依次打开不同的域以限制消耗的功率。 域的接通时间与存储器访问的等待时间重叠，使得功率控制对于访问存储器核心的用户是透明的。 存储器件可以根据所需的数据带宽在快速和慢时钟之间动态切换。 存储器接口上的数据带宽可以由存储器控制器进行监视，并且当其低于某个阈值时，可以使用较慢的时钟。 随着带宽需求的增加，时钟速度可以动态增加。
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18.发明授权Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode 有权一种存储器件和系统的操作方法，包括以第一频率进行初始化和在第二频率和掉电退出模式下的操作公开(公告)号：US08127152B2
公开(公告)日：2012-02-28
申请号：US10993046
申请日：2004-11-19
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.
摘要翻译： 在实施例中提供了存储器件和系统的操作方法。 初始化操作在初始化序列期间以第一操作频率进行。 然后在第二操作频率下执行存储器存取操作。 第二个操作频率高于第一个操作频率。 此外，存储器访问操作包括读取操作和写入操作。 在实施例中，从串行存在检测装置读取表示第一操作频率和第二操作频率的信息。
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公开(公告)号：US07574616B2
公开(公告)日：2009-08-11
申请号：US10944320
申请日：2004-09-17
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F1/26
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.
摘要翻译： 在一个实施例中，提供了一种包括存储器单元阵列的存储器件以及用于存储表示在从掉电模式恢复之前存储器件准备好接收命令之前经过一段时间的值的寄存器电路。 该命令指定对存储单元阵列的访问。 延迟锁定环路电路使用外部时钟信号同步数据传输。 延迟锁定环路电路在一段时间内重新获得与外部时钟信号的同步。
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20.发明授权公开(公告)号：US07349279B2
公开(公告)日：2008-03-25
申请号：US11562856
申请日：2006-11-22
申请人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel
发明人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel
IPC分类号： G11C7/00
CPC分类号： G11C11/40618 , G11C8/08 , G11C11/406 , G11C11/40615 , G11C11/4085 , G11C2211/4061 , G11C2211/4067
摘要： A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the memory cells located in each of the banks. Further, a refresh frequency for the refresh operation is selected such that the refresh frequency is minimized to conserve power consumed by the memory device while being sufficient to refresh the rows of the memory cells.
摘要翻译： 动态随机存取存储器件包括一组动态存储器单元。 响应于接收到自刷新命令，设备通过刷新位于每个存储体中的存储单元的行来执行刷新操作。 此外，选择刷新操作的刷新频率使得刷新频率最小化以节省存储器件消耗的功率，同时足以刷新存储器单元的行。
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