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11.发明授权公开(公告)号：US06284585B1
公开(公告)日：2001-09-04
申请号：US09387103
申请日：1999-08-31
IPC分类号： H01L218242
CPC分类号： H01L27/11521 , G11C7/18 , G11C8/12 , G11C16/0491 , H01L27/115
摘要： An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks. Also provided is a method of implementing the memory block, as organized into a matrix-like configuration, individually selectable from a plurality of blocks embedded in a memory device, wherein each memory cell is identified by a continuous bit line enabled by at least one block selector, by a broken bit line or ‘segment’ connected to the continuous one through an address device, and by a word line orthogonal to the direction of the bit lines, and formed on a substrate having a first type of conductivity.
摘要翻译： 一种电子存储器件，其组织成分为多个单元的单元及其相关联的解码和寻址电路组成的单元，该单元以预定的电路结构连接，每个单元包含在两个相互接触的区域之间， 导线称为位线。 在本发明中，通过插入用作块选择器的受控开关，在接触区域附近的每个位线中提供至少一个中断。 有利地，所提出的解决方案允许通过启用或禁用级联连接的块的开关来单独地隔离每个块。 还提供了一种实现存储块的方法，其被组织成矩阵状配置，可从嵌入在存储器设备中的多个块单独选择，其中每个存储器单元由至少一个块使能的连续位线标识 选择器，通过地址装置连接到连续的位线的断开的位线或通过与位线的方向正交的字线，并形成在具有第一类型导电性的基板上。
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12.发明授权Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substrates 失效用于在存储器件集成半导体衬底中实现字线的自动对准蚀刻工艺
公开(公告)号：US6130165A
公开(公告)日：2000-10-10
申请号：US997499
申请日：1997-12-23
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/311
CPC分类号： H01L27/11521 , H01L21/3213 , H01L21/76838
摘要： Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.
摘要翻译： 自对准蚀刻工艺，用于在由半导体衬底开始沉积的第一导电层中沉积的第一导电层中提供多个相互平行的字线，所述半导体衬底上设置有沿着分离的并行线延伸的多个有源元件，例如存储器单元位线 并且包括由第一导电层，中间电介质层和第二导电层构成的栅极区，其中所述区域通过绝缘区域彼此绝缘以形成所述结构，所述字线通过防护带光刻地限定， ：用于从第二导电层和中间介电层的第一导电层的未保护区域完全去除的垂直轮廓刻蚀，以及第一导电层的以下各向同性蚀刻。
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13.发明授权
公开(公告)号：US5969977A
公开(公告)日：1999-10-19
申请号：US998854
申请日：1997-12-29
IPC分类号： G11C7/18 , G11C8/12 , G11C16/04 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/00
CPC分类号： H01L27/11521 , G11C16/0491 , G11C7/18 , G11C8/12 , H01L27/115
摘要： An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks. Also provided is a method of implementing the memory block, as organized into a matrix-like configuration, individually selectable from a plurality of blocks embedded in a memory device, wherein each memory cell is identified by a continuous bit line enabled by at least one block selector, by a broken bit line or `segment` connected to the continuous one through an address device, and by a word line orthogonal to the direction of the bit lines, and formed on a substrate having a first type of conductivity.
摘要翻译： 一种电子存储器件，其组织成分为多个单元的单元及其相关联的解码和寻址电路组成的单元，该单元以预定的电路结构连接，每个单元包含在两个相互接触的区域之间， 导线称为位线。 在本发明中，通过插入用作块选择器的受控开关，在接触区域附近的每个位线中提供至少一个中断。 有利地，所提出的解决方案允许通过启用或禁用级联连接的块的开关来单独地隔离每个块。 还提供了一种实现存储块的方法，其被组织成矩阵状配置，可从嵌入在存储器设备中的多个块单独选择，其中每个存储器单元由至少一个块使能的连续位线标识 选择器，通过地址装置连接到连续的位线的断开的位线或“段”，以及与位线的方向正交的字线，并形成在具有第一类型导电性的基板上。
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公开(公告)号：US5440510A
公开(公告)日：1995-08-08
申请号：US86342
申请日：1993-06-30
申请人： Paolo Caprara , Emilio Camerlenghi
发明人： Paolo Caprara , Emilio Camerlenghi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/115
摘要： An integrated circuit unerasable memory cell which includes at least one memory cell consisting of a floating gate transistor with drain, source, and gate terminals, and a metallic shield embedded in the semiconductor substrate and covering the cell. Also provided are a diffused region defining a closed loop path on the substrate surface all around the transistor, and having said shield connected peripherally thereto in an unbroken fashion, and first and second wells extending in the substrate from the transistor to outside the diffused region, the first of said wells being connected directly to the gate terminal of the transistor. A contact inside the shield connects the shield's top surface to the cell's source. A protection diode (inside the shield) prevents charging of the floating gate during manufacture.
摘要翻译： 一种集成电路不可擦除存储单元，其包括由具有漏极，源极和栅极端子的浮置栅极晶体管组成的至少一个存储单元，以及嵌入在半导体衬底中并覆盖该单元的金属屏蔽。 还提供了扩散区域，其限定了晶体管周围的衬底表面上的闭环路径，并且具有以不间断的方式在其周围连接的所述屏蔽以及在衬底中从晶体管延伸到扩散区域外部的第一和第二阱， 所述阱中的第一个阱直接连接到晶体管的栅极端子。 屏蔽层内部的触点将屏蔽的顶部表面连接到电池的源头。 保护二极管（屏蔽内部）可防止浮动栅极在制造过程中充电。
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15.发明授权Non-volatile split gate EPROM memory cell and self-aligned field insulation process for obtaining the above cell 失效非挥发性分离栅EPROM存储单元和自对准的场绝缘过程，用于获取上述单元
公开(公告)号：US5241499A
公开(公告)日：1993-08-31
申请号：US631008
申请日：1990-12-19
申请人： Emilio Camerlenghi
发明人： Emilio Camerlenghi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , H01L27/115 , H01L29/7885
摘要： The cell comprises a substrate with diffusions of source and drain separated by a channel area a floating gate superimposed over a first part of said channel area and a control gate formed by a first and a second polysilicon strip, respectively, a cell gate oxide between said floating gate and said first part of the channel area, a transistor gate oxide between said control gate and a second part of the channel area, an interpoly oxide between said floating gate and said control gate and a layer of dielectric filler. By means of a process which provides for self-aligned etchings of layers of polysilicon and of oxides there is obtained a floating gate and a control gate self-aligned with one another and with the diffusions of source and drain, as well as with the first oxide.
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16.发明申请SEALING METHOD FOR ELECTRONIC DEVICES FORMED ON A COMMON SEMICONDUCTOR SUBSTRATE AND CORRESPONDING CIRCUIT STRUCTURE 审中-公开在通用半导体基板上形成的电子器件的密封方法和相应的电路结构公开(公告)号：US20070026610A1
公开(公告)日：2007-02-01
申请号：US11457948
申请日：2006-07-17
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823468 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： An integrated circuit includes a semiconductor substrate including first and second portions, with first electronic devices adjacent the first portion. Each first electronic device includes a first region comprising at least one first conductive layer projecting from the semiconductor substrate. First protective spacers are adjacent sidewalls of the first regions of the first electronic devices. The first protective spacers are defined by first and second sealing layers adjacent one another. Second electronic devices are adjacent the second portion of the semiconductor substrate. Each second electronic device includes a second region comprising a second conductive layer projecting from the semiconductor substrate. Second protective spacers are adjacent sidewalls of the second regions of the second electronic devices. The second protective spacers are defined by other portions of the second sealing layer. The second sealing layer has a thickness less than a thickness of the first sealing layer.
摘要翻译： 集成电路包括包括第一和第二部分的半导体衬底，第一电子器件与第一部分相邻。 每个第一电子器件包括包含从半导体衬底突出的至少一个第一导电层的第一区域。 第一保护间隔物是第一电子器件的第一区域的相邻侧壁。 第一保护隔离物由彼此相邻的第一和第二密封层限定。 第二电子器件与半导体衬底的第二部分相邻。 每个第二电子器件包括第二区域，其包括从半导体衬底突出的第二导电层。 第二保护间隔物是第二电子器件的第二区域的相邻侧壁。 第二保护隔离物由第二密封层的其它部分限定。 第二密封层的厚度小于第一密封层的厚度。
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17.发明授权Test structure for the measurement of contact to gate distance in non-volatile memory devices and corresponding test method 失效用于测量非易失性存储器件中接触栅极距离的测试结构和相应的测试方法公开(公告)号：US06903995B2
公开(公告)日：2005-06-07
申请号：US10449761
申请日：2003-05-30
CPC分类号： G11C29/006 , G11C16/04 , G11C29/02 , G11C29/50 , G11C2029/5002
摘要： An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.
摘要翻译： 集成的非易失性存储器件可以包括组织成行（或字线）和列（或位线），对应的行和列解码电路的存储器单元的第一矩阵，以及用于读取和修改数据的读取，修改和擦除电路 存储在存储单元中。 此外，存储器件还可以包括测试结构，其包括小于第一存储器单元的存储器单元的第二矩阵。 第二存储器矩阵可以包括每个具有与栅极距离的不同接触的字线耦合。 也就是说，每个联轴器与相应的门相比不同于相邻联接器的距离。
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公开(公告)号：US06242793B1
公开(公告)日：2001-06-05
申请号：US09231129
申请日：1998-12-30
申请人： Paolo Colombo , Emilio Camerlenghi
发明人： Paolo Colombo , Emilio Camerlenghi
IPC分类号： H01L2973
CPC分类号： H01L29/735 , H01L27/0259
摘要： A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.
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19.发明授权Voltage regulator for non-volatile semiconductor electrically programmable memory devices 失效用于非易失性半导体电子可编程存储器件的稳压器
公开(公告)号：US5905677A
公开(公告)日：1999-05-18
申请号：US831046
申请日：1997-04-01
摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.
摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 这提供了存储器件的位线上的漏极电压，其根据存储器单元的实际长度而变化。
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20.发明授权
公开(公告)号：US5682349A
公开(公告)日：1997-10-28
申请号：US454650
申请日：1995-05-31
IPC分类号： G11C17/00 , G11C16/06 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/50 , H01L27/00 , G11C11/34
CPC分类号： G11C29/82 , G11C16/34 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5006
摘要： Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults, such as low grain, in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.
摘要翻译： 由于在正常操作期间发生诸如电池增益和电池排空的降低的故障现象，本发明提出在存储器件中，行和/或列地址解码装置（RDEC，CDEC）包括至少一个非易失性存储器（NVM ），并且读写控制逻辑（CL）包括被设计用于识别存储器件的矩阵（MAT）的行和/或列中的单元故障（例如低纹理）的装置（TST），并且写入 用于在与存在于矩阵（MAT）中的冗余行和/或列（RID）对应的正常操作地址期间在所述非易失性存储器（NVM）上写入的装置（WM），以纠正所述故障。
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