公开(公告)号：US07611928B2

公开(公告)日：2009-11-03

申请号：US10968846

申请日：2004-10-18

申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Stadele

发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Stadele

IPC分类号： H01L21/00

CPC分类号： H01L21/76254

摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

摘要翻译： 衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。 第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层 并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。 在半导体层上形成晶体管。

公开(公告)号：US07598543B2

公开(公告)日：2009-10-06

申请号：US11438883

申请日：2006-05-23

申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Staedele

发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Staedele

IPC分类号： H01L27/108

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203

摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.

摘要翻译： 半导体存储器组件包括至少一个存储单元。 存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。 主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。 栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。 体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。 第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。

公开(公告)号：US07208794B2

公开(公告)日：2007-04-24

申请号：US11073017

申请日：2005-03-04

申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/905

摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.

摘要翻译： 具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中， 肋骨 肋具有基本上矩形的形状，肋的上侧和肋侧面相对。 存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个 肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。 栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。

公开(公告)号：US07700427B2

公开(公告)日：2010-04-20

申请号：US11762582

申请日：2007-06-13

申请人： Michael Specht ,  Franz Hofmann ,  Wolfgang Roesner ,  Guerkan Ilicali

发明人： Michael Specht ,  Franz Hofmann ,  Wolfgang Roesner ,  Guerkan Ilicali

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L25/0657 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66818 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure.

摘要翻译： 本发明的实施例一般涉及用于制造集成电路的方法，用于制造单元布置的方法，集成电路，单元布置和存储器模块。 在本发明的一个实施例中，提供一种用于制造具有单元布置的集成电路的方法，包括形成至少一个半导体鳍结构，其具有用于多个鳍场效应晶体管的面积，其中每个鳍场效应晶体管的面积 包括具有第一鳍结构宽度的第一区域，具有第二鳍结构宽度的第二区域，其中第二鳍结构宽度小于第一鳍结构宽度。 此外，在半导体鳍片结构的第二区域上或上方形成多个电荷存储区域。

公开(公告)号：US07560351B2

公开(公告)日：2009-07-14

申请号：US11324803

申请日：2006-01-03

申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

IPC分类号： H01L21/336

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/78 ,  Y10S438/964

摘要： An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.

摘要翻译： 提出了一种集成电路布置和制造方法。 集成电路装置包含半导体和金属电极。 使用延伸穿过半导体和电极之间的过渡层的半导体和/或电极的部分区域，增加半导体和电极之间的接触面积而不增加横向尺寸。

公开(公告)号：US07528425B2

公开(公告)日：2009-05-05

申请号：US11193026

申请日：2005-07-29

申请人： Michael Specht ,  Wolfgang Roesner ,  Franz Hofmann

发明人： Michael Specht ,  Wolfgang Roesner ,  Franz Hofmann

IPC分类号： H01L29/792

CPC分类号： H01L29/7887 ,  G11C16/0475 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/7923

摘要： A semiconductor memory having a multitude of memory cells (21-1), the semiconductor memory having a substrate (1), at least one wordline (5-1), a first (15-1) and a second line (15-2; 16-1), wherein each of the multitude of memory cells (21-1) comprises a first doping region (6) disposed in the substrate (1), a second doping region (7) disposed in the substrate (1), a channel region (22) disposed in the substrate (1) between the first doping region (6) and the second doping region (7), a charge-trapping layer stack (2) disposed on the substrate (1), on the channel region (22), on a portion of the first doping region (6) and on a portion of the second doping region (7). Each memory cell (21-1) further comprises a conductive layer (3) disposed on the charge-trapping layer stack (2), wherein the conductive layer (3) is electrically floating. A dielectric layer (4) is disposed on a top surface of the conductive layer (3) and on sidewalls (23) of the conductive layer (3). The first line (15-1) extends along a first direction and is coupled to the first doping region (6), and the second line (15-2; 16-1) extends along the first direction and is coupled to the second doping region (7). The at least one wordline (5-1) extends along a second direction and is disposed on the dielectric layer (4).

摘要翻译： 一种具有多个存储单元（21-1）的半导体存储器，所述半导体存储器具有衬底（1），至少一个字线（5-1），第一（15-1）和第二线（15-2） ; 16-1），其中多个存储单元（21-1）中的每一个包括设置在所述基板（1）中的第一掺杂区域（6），设置在所述基板（1）中的第二掺杂区域（7） 设置在第一掺杂区域（6）和第二掺杂区域（7）之间的衬底（1）中的沟道区域（22），设置在衬底（1）上的电荷捕获层堆叠（2） 在第一掺杂区域（6）的一部分上和第二掺杂区域（7）的一部分上的区域（22）。 每个存储单元（21-1）还包括设置在电荷捕获层堆叠（2）上的导电层（3），其中导电层（3）是电浮置的。 介电层（4）设置在导电层（3）的顶表面和导电层（3）的侧壁（23）上。 第一行（15-1）沿着第一方向延伸并且耦合到第一掺杂区域（6），并且第二线路（15-2; 16-1）沿第一方向延伸并耦合到第二掺杂区域 地区（7）。 所述至少一个字线（5-1）沿着第二方向延伸并设置在所述电介质层（4）上。

公开(公告)号：US20060115978A1

公开(公告)日：2006-06-01

申请号：US11000350

申请日：2004-11-30

申请人： Michael Specht ,  Wolfgang Roesner ,  Franz Hofmann

发明人： Michael Specht ,  Wolfgang Roesner ,  Franz Hofmann

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/28282 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/792

摘要： The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.

摘要翻译： 存储单元阵列包括多个平行翅片，它们设置成彼此相距约40nm的位线，并且具有小于约30nm的横向尺寸，被细分成相邻的第一和第二鳍片对。 鳍片上布置有电荷俘获记忆层序列。 词汇排列在翅片之间，源极/漏极区域位于字线之间的翅片和翅片的末端。 优选地，在鳍片的端部处的源极/漏极区域的自对准接触区域，每个接触区域对于所述成对中的一个的翅片是共同的。 选择晶体管，并且单独地为第一和第二散热片提供选择线以使得能够单独寻址存储器单元。

公开(公告)号：US20050110088A1

公开(公告)日：2005-05-26

申请号：US10968846

申请日：2004-10-18

申请人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Stadele

发明人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Stadele

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L27/01

CPC分类号： H01L21/76254

摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

摘要翻译： 衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。 第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层 并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。 在半导体层上形成晶体管。

公开(公告)号：US06420228B1

公开(公告)日：2002-07-16

申请号：US09851051

申请日：2001-05-08

申请人： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofmann

发明人： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofmann

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10841

摘要： A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks with a memory cell area of 4 F2. F is a minimum structure size which can be produced by using the respective technology.

摘要翻译： DRAM单元配置包括每个存储单元的垂直MOS晶体管。 晶体管的第一源极/漏极区域分别属于两个相邻的晶体管并与位线相邻。 晶体管的第二源/漏区连接到存储节点。 晶体管的栅电极具有由栅极氧化物邻接的正好两侧。 可以通过使用具有4F2的存储单元面积的三个掩模来产生DRAM单元配置。 F是可以通过使用各自技术制造的最小结构尺寸。

公开(公告)号：US07180115B1

公开(公告)日：2007-02-20

申请号：US10130441

申请日：2000-11-14

申请人： Franz Hofmann ,  Wolfgang Roesner ,  Lothar Risch ,  Till Schloesser

发明人： Franz Hofmann ,  Wolfgang Roesner ,  Lothar Risch ,  Till Schloesser

IPC分类号： H01L27/108

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10891 ,  H01L27/1203

摘要： The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D1). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D1) are arranged in the insulating area. The second source/drain area (S/D2) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.

摘要翻译： 本发明涉及一种具有第一源极/漏极区域（S / D 1），与其相邻的沟道区域（KA），与其相邻的第二源极/漏极区域（S / D 2），栅极电介质 和栅电极。 电容器的第一电容器电极（SP）连接到第一源极/漏极区域（S / D 1）。 绝缘结构完全围绕电路装置的绝缘区域。 至少第一电容器电极（SP）和第一源极/漏极区域（S / D 1）布置在绝缘区域中。 电容器的第二源极/漏极区域（S / D 2）和第二电容器电极布置在绝缘区域的外部。 绝缘结构防止第一电容器电极（SP）通过电容器的充电和放电之间的泄漏电流而失去电荷。 布置在通道区域（KA）中的隧道势垒（T）是绝缘结构的一部分。 将第一电容器电极（SP）与第二电容器电极分离的电容器电介质（KD）是绝缘结构的一部分。