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    Method for the production of a DRAM cell configuration
    2.
    发明授权
    Method for the production of a DRAM cell configuration 有权
    用于生产DRAM单元配置的方法

    公开(公告)号：US06420228B1

    公开(公告)日：2002-07-16

    申请号：US09851051

    申请日：2001-05-08

    申请人： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofmann

    发明人： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofmann

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks with a memory cell area of 4 F2. F is a minimum structure size which can be produced by using the respective technology.

    摘要翻译： DRAM单元配置包括每个存储单元的垂直MOS晶体管。 晶体管的第一源极/漏极区域分别属于两个相邻的晶体管并与位线相邻。 晶体管的第二源/漏区连接到存储节点。 晶体管的栅电极具有由栅极氧化物邻接的正好两侧。 可以通过使用具有4F2的存储单元面积的三个掩模来产生DRAM单元配置。 F是可以通过使用各自技术制造的最小结构尺寸。

    DRAM cell arrangement and method for its manufacture
    3.
    发明授权
    DRAM cell arrangement and method for its manufacture 失效
    DRAM单元布置及其制造方法

    公开(公告)号：US5736761A

    公开(公告)日：1998-04-07

    申请号：US645503

    申请日：1996-05-14

    申请人： Lothar Risch ,  Franz Hofmann ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    发明人： Lothar Risch ,  Franz Hofmann ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10876 ,  H01L27/10823

    摘要： The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capacitor dielectric (16), which is in particular a ferroelectric or paraelectric layer, is arranged on at least the second source/drain region and a capacitor plate (17) is arranged on the dielectric, so that the second source/drain region (3) acts additionally as a memory node. The DRAM cell arrangement can be manufactured with a memory cell surface of 4 F.sup.2.

    摘要翻译： DRAM单元布置对每个存储单元具有一个垂直MOS晶体管，其第一源极/漏极区域邻接沟槽位线（5），其栅极电极（13）与沟槽字线连接，并且其第二源极/漏极区域（3）邻接 基板主表面（1）。 至少在第二源极/漏极区域上布置有特别是铁电体或者顺电层的电容器电介质（16），并且电容器板（17）布置在电介质上，使得第二源极/漏极区域 3）另外作为存储器节点。 可以利用4F2的存储单元表面来制造DRAM单元布置。

    DRAM cell structure with tunnel barrier
    4.
    发明授权
    DRAM cell structure with tunnel barrier 有权
    具有隧道势垒的DRAM单元结构

    公开(公告)号：US07180115B1

    公开(公告)日：2007-02-20

    申请号：US10130441

    申请日：2000-11-14

    申请人： Franz Hofmann ,  Wolfgang Roesner ,  Lothar Risch ,  Till Schloesser

    发明人： Franz Hofmann ,  Wolfgang Roesner ,  Lothar Risch ,  Till Schloesser

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10891 ,  H01L27/1203

    摘要： The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D1). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D1) are arranged in the insulating area. The second source/drain area (S/D2) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.

    摘要翻译： 本发明涉及一种具有第一源极/漏极区域（S / D 1），与其相邻的沟道区域（KA），与其相邻的第二源极/漏极区域（S / D 2），栅极电介质 和栅电极。 电容器的第一电容器电极（SP）连接到第一源极/漏极区域（S / D 1）。 绝缘结构完全围绕电路装置的绝缘区域。 至少第一电容器电极（SP）和第一源极/漏极区域（S / D 1）布置在绝缘区域中。 电容器的第二源极/漏极区域（S / D 2）和第二电容器电极布置在绝缘区域的外部。 绝缘结构防止第一电容器电极（SP）通过电容器的充电和放电之间的泄漏电流而失去电荷。 布置在通道区域（KA）中的隧道势垒（T）是绝缘结构的一部分。 将第一电容器电极（SP）与第二电容器电极分离的电容器电介质（KD）是绝缘结构的一部分。

    DRAM cell configuration and method for its production
    5.
    发明授权
    DRAM cell configuration and method for its production 失效
    DRAM单元配置及其生产方法

    公开(公告)号：US06255684B1

    公开(公告)日：2001-07-03

    申请号：US09071798

    申请日：1998-05-04

    申请人： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofmann

    发明人： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofmann

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks, with a memory cell area of 4 F2. F is a minimum structure size which can be produced by using the respective technology.

    摘要翻译： DRAM单元配置包括每个存储单元的垂直MOS晶体管。 晶体管的第一源极/漏极区域分别属于两个相邻的晶体管并与位线相邻。 晶体管的第二源/漏区连接到存储节点。 晶体管的栅电极具有由栅极氧化物邻接的正好两侧。 可以通过使用具有4F2的存储单元面积的三个掩模来产生DRAM单元配置。 F是可以通过使用各自技术制造的最小结构尺寸。

    DRAM cell arrangement and method for its production
    6.
    发明授权
    DRAM cell arrangement and method for its production 有权
    DRAM单元布置及其生产方法

    公开(公告)号：US6147376A

    公开(公告)日：2000-11-14

    申请号：US228611

    申请日：1999-01-12

    申请人： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    发明人： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.

    摘要翻译： 存储单元包含至少一个晶体管和一个连接到高位线的电容器。 电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。 基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。 每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。 沟槽可以通过间隔物变窄。

    Method for manufacturing an integrated circuit arrangement having at least one MOS transistor
    8.
    发明授权
    Method for manufacturing an integrated circuit arrangement having at least one MOS transistor 有权
    一种用于制造具有至少一个MOS晶体管的集成电路装置的方法

    公开(公告)号：US06274431B1

    公开(公告)日：2001-08-14

    申请号：US09301108

    申请日：1999-04-28

    申请人： Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

    发明人： Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

    IPC分类号： H01L2976

    CPC分类号： H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66666

    摘要： An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

    摘要翻译： 集成电路装置包含由绝缘结构围绕的MOS晶体管，其源极和漏极横向排列并且在不同的深度。 其通道基本上垂直于电路装置的表面。 由于通过蚀刻或通过生长层来确定沟道长度，所以可以实现短于小于50nm的沟道长度。 为了制造，采用其中集成平面晶体管的传统电路布置的大多数掩模，这显着地有助于结合到半导体制造中。

    Method for DRAM cell arrangement and method for its production
    10.
    发明授权
    Method for DRAM cell arrangement and method for its production 有权
    DRAM单元布置方法及其制作方法

    公开(公告)号：US06184045B2

    公开(公告)日：2001-02-06

    申请号：US09541952

    申请日：2000-04-03

    申请人： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    发明人： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    IPC分类号： H01L218242

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.

    摘要翻译： 存储单元包含至少一个晶体管和一个连接到高位线的电容器。 电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。 基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。 每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。 沟槽可以通过间隔物变窄。