摘要:
Devices, methods, and systems comprising a MEMS device, for example, an interferometric modulator, that comprises a cavity in which a layer coats multiple surfaces. The layer is conformal or non-conformal. In some embodiments, the layer is formed by atomic layer deposition (ALD). Preferably, the layer comprises a dielectric material. In some embodiments, the MEMS device also exhibits improved characteristics, such as improved electrical insulation between moving electrodes, reduced stiction, and/or improved mechanical properties.
摘要:
Devices, methods, and systems comprising a MEMS device, for example, an interferometric modulator, that comprises a cavity in which a layer coats multiple surfaces. The layer is conformal or non-conformal. In some embodiments, the layer is formed by atomic layer deposition (ALD). Preferably, the layer comprises a dielectric material. In some embodiments, the MEMS device also exhibits improved characteristics, such as improved electrical insulation between moving electrodes, reduced stiction, and/or improved mechanical properties.
摘要:
A display device having an illumination system with integrated accelerometer is disclosed in which a portion of the illumination system is used as the proof mass for the accelerometer. In one embodiment, the display device includes a plurality of display elements, one or more light sources, one or more light redirectors configured to redirect at least a portion of the light generated by the light sources to at least a portion of the plurality of display elements, one or more light detectors each configured to determine a light intensity, and a processor configured to determine one or more accelerations based on the determined light intensity.
摘要:
A method for etching a target material in the presence of a structural material with improved selectivity uses a vapor phase etchant and a co-etchant. Embodiments of the method exhibit improved selectivities of from at least about 2-times to at least about 100-times compared with a similar etching process not using a co-etchant. In some embodiments, the target material comprises a metal etchable by the vapor phase etchant. Embodiments of the method are particularly useful in the manufacture of MEMS devices, for example, interferometric modulators. In some embodiments, the target material comprises a metal etchable by the vapor phase etchant, for example, molybdenum and the structural material comprises a dielectric, for example silicon dioxide.
摘要:
A capacitive MEMS device is formed having a material between electrodes that traps and retains charges. The material can be realized in several configurations. It can be a multilayer dielectric stack with regions of different band gap energies or band energy levels. The dielectric materials can be trappy itself, i.e. when defects or trap sites are pre-fabricated in the material. Another configuration involves a thin layer of a conductive material with the energy level in the forbidden gap of the dielectric layer. The device may be programmed (i.e. offset and threshold voltages pre-set) by a method making advantageous use of charge storage in the material, wherein the interferometric modulator is pre-charged in such a way that the hysteresis curve shifts, and the actuation voltage threshold of the modulator is significantly lowered. During programming phase, charge transfer between the electrodes and the materials can be performed by applying voltage to the electrodes (i.e. applying electrical field across the material) or by UV-illumination and injection of electrical charges over the energy barrier. The interferometric modulator may then be retained in an actuated state with a significantly lower actuation voltage, thereby saving power.
摘要:
The efficiency of an etching process may be increased in various ways, and the cost of an etching process may be decreased. Unused etchant may be isolated and recirculated during the etching process. Etching byproducts may be collected and removed from the etching system during the etching process. Components of the etchant may be isolated and used to general additional etchant. Either or both of the etchant or the layers being etched may also be optimized for a particular etching process.
摘要:
A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer. Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer.
摘要:
A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.
摘要:
Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.
摘要:
The present invention provides a semiconductor structure comprising a semiconductor substrate having source and drain diffusion regions located therein, the source and drain diffusion regions being separated by a device channel; and a gate stack located on top of the device channel, the gate stack comprising a high-k gate dielectric, an insulating interlayer and a fully silicided metal gate conductor, the insulating interlayer located between the high-k gate dielectric and the fully silicided metal gate conductor, wherein the insulating interlayer is capable of stabilizing threshold voltage and flatband voltage of the semiconductor structure to a targeted value.