公开(公告)号：US09007248B2

公开(公告)日：2015-04-14

申请号：US14028905

申请日：2013-09-17

申请人： Fujitsu Limited

发明人： Kazuaki Oishi

IPC分类号： H03M3/00 ,  H03M7/30

CPC分类号： H03M3/50 ,  H03M3/30 ,  H03M7/3022

摘要： A MASH sigma-delta modulator includes: parallel integration units in M stages configured to receive N pieces of data from a previous stage, to perform integral calculation in parallel; parallel differentiation units each configured to calculate a difference between neighboring overflows of the corresponding parallel integration unit of the integration part; and a parallel-to-serial conversion part configured to parallel-to-serial convert outputs from the differentiation part, wherein the parallel integration units receive pieces of input data in parallel, the parallel integration unit in each stage and the parallel differentiation unit in each stage perform integral calculation and differential calculation in each stage in one operation clock of a frequency 1/N times a master clock frequency, and the parallel-to-serial conversion part outputs the result of the parallel-to-serial conversion in synchronization with the master clock.

摘要翻译： MASHΣ-Δ调制器包括：M级并行整合单元，被配置为从前一级接收N条数据，并行执行积分计算; 每个差分单元被配置为计算积分部分的相应的并行积分单元的相邻溢出之间的差异; 以及并行到串行转换部分，其被配置为并行 - 串行转换来自所述微分部分的输出，其中所述并行整合单元并行地接收输入数据，每个级中的并行整合单元和每个中的并行微分单元 在主时钟频率的1 / N倍的一个操作时钟中的每个级中执行积分计算和差分计算，并行到串行转换部分将与并行到串行转换的结果同步地输出 主时钟。

公开(公告)号：US20150077184A1

公开(公告)日：2015-03-19

申请号：US14551501

申请日：2014-11-24

申请人： FUJITSU LIMITED

发明人： Kazuaki Oishi

IPC分类号： H03G3/30 ,  H03F3/21 ,  H03F3/193

CPC分类号： H03G3/3042 ,  H03F1/0227 ,  H03F1/3241 ,  H03F3/19 ,  H03F3/193 ,  H03F3/21 ,  H03F3/24 ,  H03F2200/165 ,  H03F2200/451

摘要： An amplifier circuit includes: a first filter that receives input of amplitude information of an input signal, and performs filtering so that a gain of a frequency component higher than a first cutoff frequency becomes greater than a gain of a frequency component lower than the first cutoff frequency; a power supply circuit that has a low-pass filter characteristic, and receives input of amplitude information outputted from the first filter and generates a power supply voltage corresponding to the amplitude information outputted from the first filter; an amplifier that receives supply of the power supply voltage, and amplifies a signal based on the input signal; and a phase difference detector that detects a phase difference between the amplitude information of the input signal and the power supply voltage, wherein the first filter changes the first cutoff frequency in a direction in which the phase difference decreases.

摘要翻译： 放大器电路包括：第一滤波器，其接收输入信号的幅度信息的输入，并且执行滤波，使得高于第一截止频率的频率分量的增益变得大于低于第一截止频率的频率分量的增益 频率; 具有低通滤波特性的电源电路，接收从第一滤波器输出的振幅信息的输入，并产生与从第一滤波器输出的振幅信息相对应的电源电压; 放大器，其接收电源电压的供应，并且基于所述输入信号放大信号; 以及相位差检测器，其检测所述输入信号的幅度信息与所述电源电压之间的相位差，其中所述第一滤波器在所述相位差减小的方向上改变所述第一截止频率。

公开(公告)号：US20190214998A1

公开(公告)日：2019-07-11

申请号：US16355488

申请日：2019-03-15

申请人： FUJITSU LIMITED

发明人： Ikuo Soga ,  Kazuaki Oishi ,  Hiroshi Matsumura ,  Yoichi Kawano ,  Yasuhiro Nakasha

IPC分类号： H03L7/081 ,  H03K5/134 ,  H03L7/089 ,  H04L7/00

CPC分类号： H03L7/0812 ,  H03K5/134 ,  H03L7/081 ,  H03L7/0891 ,  H04B1/04 ,  H04L7/0037 ,  H04L7/0091 ,  H04L7/033

摘要： A delay locked loop circuit includes a first delay circuit that includes a plurality of first delay devices and a plurality of second delay devices, the plurality of first delay devices and the plurality of second delay devices are coupled in series with each other, a second delay circuit that includes a plurality of third delay devices equal in number and identical in configuration to the plurality of second delay devices, the plurality of third delay devices are coupled in series with each other, a phase comparator that outputs a phase difference between a first delayed clock output from the first delay circuit and a second delayed clock output from the second delay circuit, a first control circuit that outputs a first control signal that controls a time, and a second control circuit that outputs a second control signal.

公开(公告)号：US10348260B2

公开(公告)日：2019-07-09

申请号：US16100271

申请日：2018-08-10

申请人： FUJITSU LIMITED

发明人： Kazuaki Oishi

IPC分类号： H03G1/00 ,  H03F1/32 ,  H03F3/45

摘要： An OTA circuit includes a first input stage that includes a first pair of transistors having sources coupled to a reference potential and converts a differential input voltage input to gates of the first pair of transistors into a first control current, a second input stage that includes a second pair of transistors having sources coupled to the reference potential and converts the differential input voltage input to gates of the second pair of transistors into a second control current, a first output circuit that generates one output current out of the differential output currents in accordance with the first control current, and a second output circuit that generates the other output current out of the differential output currents in accordance with the second control current.

公开(公告)号：US09450549B2

公开(公告)日：2016-09-20

申请号：US14631582

申请日：2015-02-25

申请人： FUJITSU LIMITED

发明人： Kazuaki Oishi

IPC分类号： H03F3/45 ,  H03F1/02

CPC分类号： H03F3/45179 ,  H03F1/0211 ,  H03F1/0272 ,  H03F3/45085 ,  H03F3/45197 ,  H03F3/45659 ,  H03F3/45748 ,  H03F2200/144 ,  H03F2203/45118 ,  H03F2203/45418 ,  H03F2203/45434 ,  H03F2203/45481 ,  H03F2203/45512 ,  H03F2203/45526 ,  H03F2203/45528 ,  H03F2203/45631 ,  H03F2203/45694 ,  H03F2203/45702

摘要： A differential amplification circuit includes: a first input node; a second input node; a first output node; a second output node; a first transistor having a gate coupled to the first input node and a source coupled to a first node; a second transistor having a gate coupled to the second input node; a third transistor having a drain coupled to a drain of the first transistor; a fourth transistor having a gate coupled to a gate of the third transistor; a first resistor; a second resistor; a fifth transistor having a gate coupled to the drain of the first transistor; a sixth transistor having a gate coupled to the drain of the second transistor; a seventh transistor having a source coupled to the first node; an eighth transistor having a gate coupled to a gate of the seventh transistor; a third resistor; and a fourth resistor.

摘要翻译： 差分放大电路包括：第一输入节点; 第二输入节点; 第一输出节点; 第二输出节点; 第一晶体管，具有耦合到第一输入节点的栅极和耦合到第一节点的源极; 第二晶体管，具有耦合到第二输入节点的栅极; 第三晶体管，具有耦合到所述第一晶体管的漏极的漏极; 第四晶体管，具有耦合到第三晶体管的栅极的栅极; 第一个电阻; 第二电阻器; 第五晶体管，具有耦合到第一晶体管的漏极的栅极; 第六晶体管，其具有耦合到所述第二晶体管的漏极的栅极; 第七晶体管，具有耦合到所述第一节点的源极; 第八晶体管，具有耦合到第七晶体管的栅极的栅极; 第三电阻; 和第四电阻器。

公开(公告)号：US09225288B2

公开(公告)日：2015-12-29

申请号：US14167827

申请日：2014-01-29

申请人： FUJITSU LIMITED ,  FUJITSU SEMICONDUCTOR LIMITED

发明人： Kazuaki Oishi ,  Masahiro Kudo ,  Kotaro Murakami

IPC分类号： G06F7/44 ,  G06G7/16 ,  H03D7/14 ,  H03D5/00

CPC分类号： H03D7/1483 ,  H03D5/00 ,  H03D7/1441 ,  H03D7/1466

摘要： A signal generation circuit includes a limiter and a mixer. The limiter receives an input signal, allows the input signal to be off a scale at a limit voltage, and generates a phase signal indicating a phase component of the input signal. The mixer receives the input signal and the phase signal, and generates an amplitude signal indicating an amplitude component of the input signal.

摘要翻译： 信号发生电路包括限幅器和混频器。 限幅器接收输入信号，允许输入信号在极限电压下达到标尺，并产生指示输入信号的相位分量的相位信号。 混合器接收输入信号和相位信号，并产生指示输入信号的振幅分量的振幅信号。

公开(公告)号：US08872582B2

公开(公告)日：2014-10-28

申请号：US14284035

申请日：2014-05-21

申请人： Fujitsu Limited

发明人： Kazuaki Oishi

IPC分类号： H03G3/20 ,  H03F3/193 ,  H03F3/21 ,  H03F1/02

CPC分类号： H03F1/0216 ,  H03F1/0222 ,  H03F3/193 ,  H03F3/21 ,  H03F3/217 ,  H03F2200/102 ,  H03F2200/432 ,  H03F2200/451

摘要： An amplifier circuit includes: a first filter that receives input of amplitude information of an input signal, and performs filtering so that a gain of a frequency component higher than a first cutoff frequency becomes greater than a gain of a frequency component lower than the first cutoff frequency; a power supply circuit that has a low-pass filter characteristic that a gain of a frequency component lower than a second cutoff frequency is greater than a gain of a frequency component higher than the second cutoff frequency, and receives input of amplitude information outputted from the first filter and generates a power supply voltage corresponding to the amplitude information outputted from the first filter; and an amplifier that receives supply of the power supply voltage generated by the power supply circuit, and amplifies a signal based on the input signal.

摘要翻译： 放大器电路包括：第一滤波器，其接收输入信号的幅度信息的输入，并且执行滤波，使得高于第一截止频率的频率分量的增益变得大于低于第一截止频率的频率分量的增益 频率; 电源电路，其具有低于第二截止频率的频率分量的增益大于高于第二截止频率的频率分量的增益的低通滤波特性，并且接收从所述第二截止频率输出的频率分量的输入， 产生与从第一滤波器输出的振幅信息相对应的电源电压; 以及放大器，其接收由所述电源电路产生的电源电压的供应，并且基于所述输入信号放大信号。

公开(公告)号：US20140285243A1

公开(公告)日：2014-09-25

申请号：US14179199

申请日：2014-02-12

申请人： FUJITSU SEMICONDUCTOR LIMITED ,  FUJITSU LIMITED

发明人： Hiroyuki NAKAMOTO ,  Kazuaki Oishi ,  Tomokazu Kojima

IPC分类号： H03K17/22

CPC分类号： H03K17/223 ,  H03K3/0375 ,  H03K17/22

摘要： A power on reset circuit including: a startup circuit keeping an operation signal in an operating state during a power supply rises; a bias circuit keeping the operation signal in the operating state; a BGR circuit being activated during the operating state, and outputting a fixed voltage after a predetermined time elapses; a power supply divided voltage generation circuit outputting a reference voltage; an activation detection circuit generating a control signal which becomes inactive when a power supply rises and becomes active when the fixed voltage reaches a predetermined level; a comparator circuit outputting a power on signal and detecting as the power on signal when the reference voltage is greater than the fixed voltage; and a switch turning on and fixing an output of the comparator circuit to an inactive logical value while the control signal is inactive, and turning off while the control signal is active.

摘要翻译： 一种上电复位电路，包括：在电源上升期间保持操作信号处于工作状态的启动电路; 偏置电路，保持操作信号处于工作状态; BGR电路在工作状态下被激活，并经过预定时间后输出固定电压; 输出参考电压的电源分压电压产生电路; 激活检测电路，产生当电源上升时变得无效的控制信号，并且当固定电压达到预定电平时变为有效; 输出上电信号的比较器电路，当所述基准电压大于所述固定电压时，检测为所述上电信号; 并且当控制信号不活动时，开关导通并将比较器电路的输出固定为无效逻辑值，并且在控制信号有效时关闭。

公开(公告)号：US09614440B2

公开(公告)日：2017-04-04

申请号：US14082589

申请日：2013-11-18

申请人： FUJITSU LIMITED

发明人： Kazuaki Oishi ,  Eiji Yoshida ,  Yasufumi Sakai

IPC分类号： H02M3/158 ,  H02M3/156 ,  G05F1/46 ,  H03F1/02 ,  H02M1/00

CPC分类号： H02M3/1563 ,  G05F1/46 ,  H02M3/1584 ,  H02M2001/0045 ,  H03F1/0222

摘要： A power supply device includes a linear regulator including an output stage amplifier, a current sensing circuit, and a switching regulator. The current sensing circuit detects an output current of the linear regulator, and is disposed in parallel with the output stage amplifier, in a configuration corresponding to the output stage amplifier. The switching regulator operates in accordance with an output signal of the current sensing circuit. The linear regulator and the switching regulator operate in collaboration with each other to generate an output voltage at an output node.

公开(公告)号：US20160357623A1

公开(公告)日：2016-12-08

申请号：US15149366

申请日：2016-05-09

申请人： FUJITSU LIMITED

发明人： Kazuaki Oishi ,  Yuuichi NAMAI ,  Yukihiko HODOHARA ,  Susumu Taneoka ,  Katsuya KITAMORI ,  Kazuhiko Kobayashi ,  Naohiro WAKABAYASHI

IPC分类号： G06F11/07

CPC分类号： G06F11/0757 ,  G06F11/0715 ,  G06F11/079 ,  G06F11/30

摘要： A processor activates a first monitoring process for initializing a timer and a second monitoring process with higher priority than the first monitoring process. The processor executes the second monitoring process to monitor whether the first monitoring process has been executed. When determining that the first monitoring process has not been executed, the processor executing the second monitoring process determines whether the load state of the processor satisfies prescribed conditions. If the load state satisfies the prescribed conditions, the processor executing the second monitoring process initializes the timer.

摘要翻译： 处理器激活用于初始化定时器的第一监视处理和具有比第一监视处理更高优先级的第二监视处理。 处理器执行第二监视处理以监视第一监视处理是否已经被执行。 当确定没有执行第一监视处理时，执行第二监视处理的处理器确定处理器的负载状态是否满足规定条件。 如果负载状态满足规定条件，则执行第二监视处理的处理器初始化定时器。