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公开(公告)号：US11770142B2
公开(公告)日：2023-09-26
申请号：US17500996
申请日：2021-10-14
申请人： FUJITSU LIMITED
发明人： Kazuaki Oishi
CPC分类号： H04B1/0475 , H01Q21/065 , H04B2001/0416
摘要： A wireless communication apparatus includes a signal terminal which receives a transmitting signal, N antenna elements, where N is an integer greater than or equal to 2, a first amplifier including first input and output terminals, and N second amplifiers including N second input and output terminals coupled to the N antenna elements, respectively. The first amplifier amplifies the transmitting signal received from the signal terminal via the first input terminal with a gain which is weighted and adjustable according to a first weight. The N second amplifiers amplify the amplified transmitting signal received from the second output terminal via the N second input terminals with gains which are weighted and adjustable according to N second weights. The amplified transmitting signal, amplified by the N second amplifiers, is output to the N antenna elements via the N second output terminals.
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公开(公告)号：US20190068148A1
公开(公告)日：2019-02-28
申请号：US16100271
申请日：2018-08-10
申请人： FUJITSU LIMITED
发明人： Kazuaki Oishi
CPC分类号： H03G1/0029 , H03F1/3211 , H03F3/45179 , H03F3/45192 , H03F3/45197 , H03F3/45273 , H03F3/45475 , H03F3/45659 , H03F2200/171 , H03F2203/45 , H03F2203/45138 , H03F2203/45512 , H03F2203/45521
摘要： An OTA circuit includes a first input stage that includes a first pair of transistors having sources coupled to a reference potential and converts a differential input voltage input to gates of the first pair of transistors into a first control current, a second input stage that includes a second pair of transistors having sources coupled to the reference potential and converts the differential input voltage input to gates of the second pair of transistors into a second control current, a first output circuit that generates one output current out of the differential output currents in accordance with the first control current, and a second output circuit that generates the other output current out of the differential output currents in accordance with the second control current.
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公开(公告)号：US20180287572A1
公开(公告)日：2018-10-04
申请号：US15925367
申请日：2018-03-19
申请人： FUJITSU LIMITED
发明人： Kazuaki Oishi
摘要： A power source circuit includes a linear regulator including: an amplifier configured to amplify an envelope signal for representing an envelope of an input signal input into a power amplifier, and an output stage including transistors, configured to output power output to be supplied to the power amplifier in accordance with amplified output of the amplifier; a monitor circuit configured to monitor the envelope signal; and a switched-capacitor circuit configured to generate a power source voltage higher than a voltage of the power output based on a monitoring result of the monitor circuit, wherein the switched-capacitor circuit does not supply the power source voltage to the amplifier, but supplies the power source voltage to the output stage.
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公开(公告)号：US20180097389A1
公开(公告)日：2018-04-05
申请号：US15711263
申请日：2017-09-21
申请人： FUJITSU LIMITED
发明人： Kazuaki Oishi
IPC分类号： H02J7/00
CPC分类号： H02J7/0068 , H01M2220/30 , H02J7/0004 , H02J7/0031 , H02J7/34
摘要： An electronic apparatus includes: a load; a first battery; a second battery; and a power supply control circuit configured to couple the first battery and the second battery to the load, wherein the power supply control circuit includes: a first switch including one end coupled to the first battery and the other end coupled to the load; a second switch including one end coupled to the second battery and the other end coupled to the load; and a first comparison circuit including a first input terminal coupled to an output terminal of the first battery and a second input terminal coupled to a threshold voltage and configured to control the first switch and the second switch based on a comparison result of an output voltage of the first battery and the threshold voltage and output a first battery selection signal indicating whether the first battery powers the load.
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公开(公告)号：US20220231713A1
公开(公告)日：2022-07-21
申请号：US17500996
申请日：2021-10-14
申请人： FUJITSU LIMITED
发明人： Kazuaki Oishi
摘要： A wireless communication apparatus includes a signal terminal which receives a transmitting signal, N antenna elements, where N is an integer greater than or equal to 2, a first amplifier including first input and output terminals, and N second amplifiers including N second input and output terminals coupled to the N antenna elements, respectively. The first amplifier amplifies the transmitting signal received from the signal terminal via the first input terminal with a gain which is weighted and adjustable according to a first weight. The N second amplifiers amplify the amplified transmitting signal received from the second output terminal via the N second input terminals with gains which are weighted and adjustable according to N second weights. The amplified transmitting signal, amplified by the N second amplifiers, is output to the N antenna elements via the N second output terminals.
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公开(公告)号：US20190207646A1
公开(公告)日：2019-07-04
申请号：US16298486
申请日：2019-03-11
申请人： FUJITSU LIMITED
发明人： Ikuo SOGA , Kazuaki Oishi , Hiroshi Matsumura , Yoichi Kawano , Yasuhiro Nakasha
IPC分类号： H04B1/717 , H04B1/7163 , H04L25/49 , H03K5/135 , H03K5/133
CPC分类号： H04B1/7174 , H03K5/133 , H03K5/134 , H03K5/135 , H04B1/71637 , H04L25/49 , H04L25/4902
摘要： A pulse position modulation circuit includes a delay path that includes a plurality of delay devices coupled in series with each other, a clock being passed through the plurality of delay devices, and a switching circuit that changes a time by which the clock is delayed in each of the plurality of delay devices according to input data.
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公开(公告)号：US09099977B2
公开(公告)日：2015-08-04
申请号：US14551501
申请日：2014-11-24
申请人： FUJITSU LIMITED
发明人： Kazuaki Oishi
CPC分类号： H03G3/3042 , H03F1/0227 , H03F1/3241 , H03F3/19 , H03F3/193 , H03F3/21 , H03F3/24 , H03F2200/165 , H03F2200/451
摘要： An amplifier circuit includes: a first filter that receives input of amplitude information of an input signal, and performs filtering so that a gain of a frequency component higher than a first cutoff frequency becomes greater than a gain of a frequency component lower than the first cutoff frequency; a power supply circuit that has a low-pass filter characteristic, and receives input of amplitude information outputted from the first filter and generates a power supply voltage corresponding to the amplitude information outputted from the first filter; an amplifier that receives supply of the power supply voltage, and amplifies a signal based on the input signal; and a phase difference detector that detects a phase difference between the amplitude information of the input signal and the power supply voltage, wherein the first filter changes the first cutoff frequency in a direction in which the phase difference decreases.
摘要翻译： 放大器电路包括：第一滤波器，其接收输入信号的幅度信息的输入，并且执行滤波，使得高于第一截止频率的频率分量的增益变得大于低于第一截止频率的频率分量的增益 频率; 具有低通滤波特性的电源电路，接收从第一滤波器输出的振幅信息的输入，并产生与从第一滤波器输出的振幅信息相对应的电源电压; 放大器，其接收电源电压的供应，并且基于所述输入信号放大信号; 以及相位差检测器，其检测所述输入信号的幅度信息与所述电源电压之间的相位差，其中所述第一滤波器在所述相位差减小的方向上改变所述第一截止频率。
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8.发明授权Signal generator circuit and radio transmission and reception device including the same 有权信号发生器电路和包括其的无线电发射和接收装置公开(公告)号：US08938204B2
公开(公告)日：2015-01-20
申请号：US13733620
申请日：2013-01-03
申请人： Fujitsu Limited
发明人： Kazuaki Oishi
CPC分类号： H04B1/403 , H03B21/01 , H03B21/02 , H04B1/0082
摘要： The disclosed signal generator circuit has a four-phase signal generator circuit generating four-phase signals with a first frequency; an eight-phase signal generator circuit performing ½ frequency division of the four-phase signals to generate eight-phase signals with a second frequency; a first to a fourth harmonic rejection mixer circuits multiplying a first four-phase signal and a second four-phase signal of the four-phase signals by a first to a third eight-phase signals and a third to a fifth eight-phase signals of the eight-phase signals with mutually different combinations; a subtractor subtracting between outputs of the first and the fourth harmonic rejection mixer circuits to generate a first output signal with a third frequency; and an adder adding between outputs of the second and the third harmonic rejection mixer circuits to generate a second output signal with a third frequency whose phase is different from the first output signal by π/2.
摘要翻译： 所公开的信号发生器电路具有产生具有第一频率的四相信号的四相信号发生器电路; 执行四相信号的1/2分频以产生具有第二频率的八相信号的八相信号发生器电路; 第一至第四谐波抑制混频器电路将四相信号的第一四相信号和第二四相信号乘以第一至第三八相信号和第三至第五八相八位信号 具有相互不同组合的八相信号; 减法器，在第一和第四谐波抑制混频器电路的输出之间减去以产生具有第三频率的第一输出信号; 以及加法器，其在第二和第三谐波抑制混频器电路的输出之间相加，以产生具有第三频率的第二输出信号，该第三频率的相位与第一输出信号不同于＆pgr / / 2。
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公开(公告)号：US10050587B2
公开(公告)日：2018-08-14
申请号：US15446821
申请日：2017-03-01
申请人： FUJITSU LIMITED
摘要： A power amplifier circuit includes unit amplifiers (unit PAs) whose output terminals are connected to one another, among which a number of unit PAs to be operated is controlled by an amplitude signal indicative of an amplitude of an input signal, and which output output signals based on a phase signal indicative of a phase of the input signal and an output current controller which controls an output current of each of the unit PAs. Each unit PA includes a first transistor and a second transistor connected in series between the output terminal and a ground. The first transistor receives the phase signal at a gate. The second transistor receives at a gate a control signal generated by the output current controller and determines the output current flowing to the output terminal on the basis of the control signal.
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公开(公告)号：US09807689B2
公开(公告)日：2017-10-31
申请号：US14868232
申请日：2015-09-28
申请人： FUJITSU LIMITED
发明人： Kazuaki Oishi , Hiroyuki Sato
IPC分类号： H04W52/02
CPC分类号： H04W52/0225 , H04W52/0229 , H04W52/0245 , Y02D70/00
摘要： A communication device includes a receiving circuit and a start-up time adjustment circuit configured to transmit, to the receiving circuit, a start signal that instructs a change from a sleep state to an active state, wherein the start-up time adjustment circuit is configured to transmit, to the receiving circuit, a first start signal that instructs a change from the sleep state to the active state at a first time earlier than a second time when a first signal reaches the communication device, measure a first time difference between the second time and the first time, determine, based on the first time difference, a third time when the receiving circuit is changed from the active state to the sleep state, and transmit a second start signal that instructs a change from the sleep state to the active state to the receiving circuit at the third time.
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