公开(公告)号：US20180006140A1

公开(公告)日：2018-01-04

申请号：US15196335

申请日：2016-06-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Jody Fronheiser ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Balasubramanian Pranatharthiharan ,  Mark Raymond ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/285 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L21/76895 ,  H01L21/02068 ,  H01L21/285 ,  H01L21/28525 ,  H01L21/76814 ,  H01L21/76831 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/785

Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.

公开(公告)号：US09647086B2

公开(公告)日：2017-05-09

申请号：US14826803

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporations ,  STMicroelectronics, Inc.

Inventor： Steven Bentley ,  Jody Fronheiser ,  Xin Miao ,  Joseph Washington ,  Pierre Morin

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L29/66537 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165

Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.

公开(公告)号：US09564486B2

公开(公告)日：2017-02-07

申请号：US14839378

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。

公开(公告)号：US20160013296A1

公开(公告)日：2016-01-14

申请号：US14860276

申请日：2015-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody Fronheiser ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/267 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.

Abstract translation: 本文公开的一个示例性器件包括形成在由第一半导体材料构成的衬底中的衬底鳍片，其中衬底鳍片的至少一个侧壁基本上位于衬底的晶体结构的<100>晶体方向上，替换鳍片 位于所述衬底翅片上方的结构，其中所述替换翅片结构由与所述第一半导体材料不同的半导体材料和位于所述替换翅片结构的至少一部分周围的栅极结构构成。

公开(公告)号：US20150137308A1

公开(公告)日：2015-05-21

申请号：US14083571

申请日：2013-11-19

Applicant: International Business Machines Corporation ,  Renesas Electronics Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

公开(公告)号：US20140264488A1

公开(公告)日：2014-09-18

申请号：US13839998

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody Fronheiser ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/267 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.

Abstract translation: 本文公开的一个示例性器件包括形成在由第一半导体材料构成的衬底中的衬底鳍片，其中衬底鳍片的至少一个侧壁基本上位于衬底的晶体结构的<100>晶体方向上，替换鳍片 位于所述衬底翅片上方的结构，其中所述替换翅片结构由与所述第一半导体材料不同的半导体材料和位于所述替换翅片结构的至少一部分周围的栅极结构构成。

公开(公告)号：US09882052B2

公开(公告)日：2018-01-30

申请号：US15197892

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Judson Holt ,  Jinping Liu ,  Jody Fronheiser ,  Bharat Krishnan ,  Churamani Gaire ,  Timothy James McArdle ,  Murat Kerem Akarvardar

IPC: H01L21/335 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US09679972B1

公开(公告)日：2017-06-13

申请号：US15133683

申请日：2016-04-20

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Jody Fronheiser ,  Murat Kerem Akarvardar ,  Stephen Bedell ,  Joel Kanyandekwe

IPC: H01L29/775 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/165 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/78 ,  H01L29/7849

Abstract: A semiconductor structure can include a substrate and a substrate layer. The substrate can be formed of silicon and the substrate layer can be formed of silicon germanium. Above the substrate and under the substrate layer there can be provided a multilayer substructure. The multilayer substructure can include a first layer and a second layer. The first layer can be formed of a first material and the second layer can be formed of second material. A method can include forming a multilayer substructure on a substrate, annealing the multilayer substructure, and forming a substrate layer on the multilayer substructure.

公开(公告)号：US09614058B2

公开(公告)日：2017-04-04

申请号：US14860276

申请日：2015-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody Fronheiser ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/267 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.

公开(公告)号：US09324790B2

公开(公告)日：2016-04-26

申请号：US14083571

申请日：2013-11-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Renesas Electronics Corporation

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。