公开(公告)号：US09324869B1

公开(公告)日：2016-04-26

申请号：US14613425

申请日：2015-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L29/10 ,  H01L21/762 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

Abstract: The present disclosure provides, in various aspects, a method of forming a semiconductor device and accordingly formed semiconductor devices. In accordance with some illustrative embodiments herein, a fin is provided in an upper surface of a substrate, the fin having a height dimension and an initial width dimension. After forming a mask on the fin, wherein the mask only partially covers an upper surface of the fin, the fin is exposed to an etch process for removing material in accordance with the mask such that a channel portion connecting end portions of the fin is formed. Herein, a width dimension of the channel portion is smaller than a width dimension of the end portions. In accordance with some illustrative embodiments of the present disclosure, the channel portion may substantially have a cross-section of one of a triangular shape and a double-sigma shape.

Abstract translation: 本公开在各个方面提供了一种形成半导体器件并相应地形成的半导体器件的方法。 根据这里的一些说明性实施例，在衬底的上表面中设置翅片，翅片具有高度尺寸和初始宽度尺寸。 在翅片上形成掩模之后，其中掩模仅部分地覆盖翅片的上表面，翅片暴露于根据掩模去除材料的蚀刻工艺，使得形成连接翅片的端部的通道部分 。 这里，通道部分的宽度尺寸小于端部的宽度尺寸。 根据本公开的一些示例性实施例，通道部分可以基本上具有三角形形状和双西格玛形状之一的横截面。

公开(公告)号：US09136266B2

公开(公告)日：2015-09-15

申请号：US13943229

申请日：2013-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/513 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/78

Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.

Abstract translation: 在各个方面，提供了形成半导体器件和半导体器件的方法。 在本文的一些说明性实施例中，硅/锗层设置在半导体衬底上。 在硅/锗层上形成至少一个绝缘材料层。 在进行热退火处理之后，在随后的处理顺序中除去至少一个绝缘材料层，使得硅/锗层至少部分暴露。 在随后施加的另外的处理顺序中，在暴露的硅/锗层上形成栅电极。

公开(公告)号：US20140264347A1

公开(公告)日：2014-09-18

申请号：US13799741

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas Sassiat ,  Carsten Grass ,  Jan Hoentschel ,  Ran Yan ,  Ralf Richter

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/6675

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract translation: 当在半导体器件的有源区域中形成空腔以引入应变诱导半导体材料时，可以通过使用非晶化过程和热处理来实现空腔的改进形状，以便选择性地改变暴露部分的蚀刻行为 活性区域并调整非晶区域的形状。 以这种方式，可以以高度的灵活性来调节空腔的基本构造。 因此，可以提高应变诱导技术的效率。

公开(公告)号：US20180366579A1

公开(公告)日：2018-12-20

申请号：US15622591

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Ming-Cheng Chang ,  Thomas Merbeth

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L29/08 ,  H01L21/84

Abstract: A high voltage transistor may be formed on the basis of CMOS techniques for forming sophisticated SOI devices, wherein a fully depleted channel portion may result in low on-resistance and high breakdown voltage. Thus, an LDMOS-type transistor may be formed on the basis of a fully depleted drift region, thereby providing a high degree of scalability and process compatibility with sophisticated CMOS techniques.

公开(公告)号：US09881841B2

公开(公告)日：2018-01-30

申请号：US15074483

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alban Zaka ,  Ran Yan ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L21/268 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

公开(公告)号：US20160300947A1

公开(公告)日：2016-10-13

申请号：US14680172

申请日：2015-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides, in a first aspect, a semiconductor device including an SOI substrate portion, a gate structure formed on the SOI substrate portion and source and drain regions having respective source and drain height levels, wherein the source and drain height levels are different. The semiconductor device may be formed by forming a gate structure over an SOI substrate portion, recessing the SOI substrate portion at one side of the gate structure so as to form a trench adjacent to the gate structure and forming source and drain regions at opposing sides of the gate structure, one of the source and drain regions being formed in the trench.

Abstract translation: 本公开在第一方面提供了一种半导体器件，其包括SOI衬底部分，形成在SOI衬底部分上的栅极结构以及具有各自的源极和漏极高度水平的源极和漏极区域，其中源极和漏极高度水平是不同的 。 可以通过在SOI衬底部分上形成栅极结构来形成半导体器件，在栅极结构的一侧凹入SOI衬底部分，以形成与栅极结构相邻的沟槽，并在栅极结构的相对侧形成源极和漏极区域 栅极结构，其中一个源极和漏极区域形成在沟槽中。

公开(公告)号：US20160204038A1

公开(公告)日：2016-07-14

申请号：US15074483

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alban Zaka ,  Ran Yan ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L21/268 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供在半导体衬底上形成的具有n沟道栅极叠层和p沟道栅叠层的结构。 该方法包括在邻近p沟道栅极叠层的半导体衬底中形成卤素注入区，并在邻近p沟道栅叠层的半导体衬底中形成延伸注入区。 该方法还包括使邻近p沟道栅叠层的卤素注入区域和半导体衬底中的延伸注入区域退火。 此外，该方法在邻近n沟道栅叠层的半导体衬底中形成延伸注入区。

公开(公告)号：US09190516B2

公开(公告)日：2015-11-17

申请号：US14186387

申请日：2014-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Stefan Flachowsky ,  Alban Zaka ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/167 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/045 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66636

Abstract: A methodology for forming a compressive strain layer with increased thickness that exhibits improved device performance and the resulting device are disclosed. Embodiments may include forming a recess in a source or drain region of a substrate, implanting a high-dose impurity in a surface of the recess, and depositing a silicon-germanium (SiGe) layer in the recess.

Abstract translation: 公开了一种用于形成具有提高的器件性能的具有增加的厚度的压缩应变层的方法以及所得到的器件。 实施例可以包括在衬底的源极或漏极区域中形成凹陷，在凹部的表面中注入高剂量杂质，以及在凹部中沉积硅 - 锗（SiGe）层。

公开(公告)号：US09087716B2

公开(公告)日：2015-07-21

申请号：US13942034

申请日：2013-07-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Joerg Schoenekess ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66477

Abstract: The present disclosure provides an improved method for forming a thin semiconductor alloy layer on top of a semiconductor layer. The proposed method relies on an implantation of appropriate impurity species before performing deposition of the semiconductor alloy film. The implanted species cause the semiconductor alloy layer to be less unstable to wet and dry etches performed on the device surface after deposition. Thus, the thickness uniformity of the semiconductor alloy film may be substantially increased if the film is deposited after performing the implantation. On the other hand, some implanted impurities have been found to decrease the growth rate of the semiconductor alloy layer. Thus, by selectively implanting appropriate impurities in predetermined portions of a wafer, a single deposition step may be used in order to form a semiconductor alloy layer with a thickness which may be locally adjusted at will.

Abstract translation: 本公开提供了一种用于在半导体层的顶部上形成薄半导体合金层的改进方法。 所提出的方法依赖于在进行半导体合金膜的沉积之前植入适当的杂质物质。 植入的物质导致半导体合金层在沉积后在器件表面上进行的湿法干蚀刻不太稳定。 因此，如果在进行植入之后沉积膜，则半导体合金膜的厚度均匀性可以显着增加。 另一方面，已经发现一些植入的杂质降低了半导体合金层的生长速率。 因此，通过在晶片的预定部分中选择性地注入适当的杂质，可以使用单个沉积步骤以形成具有可以随意局部调整的厚度的半导体合金层。

公开(公告)号：US10134730B2

公开(公告)日：2018-11-20

申请号：US15642507

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/306 ,  H01L21/3213

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the semiconductor layer extending in parallel to each other along a first direction parallel to the surface of the semiconductor layer, and forming a plurality of gate electrodes comprising longitudinal portions extending parallel to the semiconductor fins along the first direction.