公开(公告)号：US10049944B2

公开(公告)日：2018-08-14

申请号：US15285978

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Scott Beasor ,  Jeremy A. Wahl

IPC: H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.

公开(公告)号：US20160049490A1

公开(公告)日：2016-02-18

申请号：US14924151

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy Wei

IPC: H01L29/45 ,  H01L27/092

CPC classification number: H01L29/45 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/41725

Abstract: Integrated circuits with dual silicide contacts are provided. In an embodiment, an integrated circuit includes a semiconductor substrate including a first area and a second area. The integrated circuit includes a first source/drain region in and/or overlying the first area of the semiconductor substrate and a second source/drain region in and/or overlying the second area of the semiconductor substrate. The integrated circuit further includes a first contact over the first source/drain region and comprising a first metal silicide. The integrated circuit also includes a second contact over the second source/drain region and comprising a second metal silicide different from the first metal silicide.

Abstract translation: 提供了具有双硅化物触点的集成电路。 在一个实施例中，集成电路包括包括第一区域和第二区域的半导体衬底。 集成电路包括位于半导体衬底的第一区域内和/或覆盖半导体衬底的第一区域的第一源极/漏极区域和位于半导体衬底的第二区域内和/或覆盖半导体衬底的第二区域中的第二源极/漏极区域。 集成电路还包括在第一源极/漏极区域上的第一接触并且包括第一金属硅化物。 集成电路还包括在第二源极/漏极区域上的第二接触并且包括不同于第一金属硅化物的第二金属硅化物。

公开(公告)号：US20150214059A1

公开(公告)日：2015-07-30

申请号：US14166660

申请日：2014-01-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/28 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/2807 ,  H01L21/28158 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

Abstract: Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.

Abstract translation: 提供了具有金属 - 绝缘体半导体（MIS）接触结构的集成电路以及用于制造具有金属 - 绝缘体 - 半导体（MIS））接触结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供由半导体材料覆盖在半导体衬底上形成的鳍结构。 该方法包括在鳍结构上沉积高k电介质材料层。 此外，该方法包括在高k电介质材料层上形成金属层，以使鳍结构具有金属 - 绝缘体半导体（MIS）接触结构。

公开(公告)号：US08969207B2

公开(公告)日：2015-03-03

申请号：US13798690

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerard M. Schmid ,  Jeremy A. Wahl ,  Richard A. Farrell ,  Chanro Park

IPC: H01L21/311 ,  H01L23/48 ,  H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.

Abstract translation: 本文公开的一种说明性方法包括形成由结构上方的多个离散开口组成的图案化的硬掩模层，其中所述图案化的硬掩模层由多个相交的线型特征组成，在图案化硬的上方形成图案化的蚀刻掩模 掩模层，其暴露多个离散开口中的至少一个但不是全部，并且通过图案化的蚀刻掩模和图案化的硬掩模层中的至少一个暴露的开口进行至少一个蚀刻工艺，以在 结构体。

公开(公告)号：US08853019B1

公开(公告)日：2014-10-07

申请号：US13798616

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody A. Fronheiser ,  Jeremy A. Wahl ,  Kerem Akarvardar ,  Ajey P. Jacob ,  Daniel T. Pham

IPC: H01L29/94 ,  H01L29/66 ,  B82Y40/00

CPC classification number: H01L29/42392 ,  B82Y40/00 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成具有至少30％的锗浓度的硅/锗层，形成多个间隔开的沟槽，其延伸穿过硅/锗层并且至少部分地进入半导体 衬底，其中所述沟槽限定由所述衬底的一部分和所述硅/锗层的一部分组成的器件的鳍结构，所述硅/锗层的所述部分具有第一横截面构造，形成层 的绝缘材料在沟槽中并在鳍结构之上，对器件进行退火处理，以使硅/锗层的第一截面构型变为不同于第二截面结构 第一横截面构造，以及围绕具有第二横截面的硅/锗层的至少一部分形成最终栅极结构 功能配置

公开(公告)号：US20140273473A1

公开(公告)日：2014-09-18

申请号：US13798690

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gerard M. Schmid ,  Jeremy A. Wahl ,  Richard A. Farrell ,  Chanro Park

IPC: H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.

Abstract translation: 本文公开的一种说明性方法包括形成由结构上方的多个离散开口组成的图案化的硬掩模层，其中所述图案化的硬掩模层由多个相交的线型特征组成，在图案化硬的上方形成图案化的蚀刻掩模 掩模层，其暴露多个离散开口中的至少一个但不是全部，并且通过图案化的蚀刻掩模和图案化的硬掩模层中的至少一个暴露的开口进行至少一个蚀刻工艺，以在 结构体。

公开(公告)号：US20200227308A1

公开(公告)日：2020-07-16

申请号：US16246847

申请日：2019-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl ,  Vimal K. Kamineni

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.

公开(公告)号：US09660075B2

公开(公告)日：2017-05-23

申请号：US15051734

申请日：2016-02-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/84 ,  H01L29/78 ,  H01L27/092 ,  H01L21/311 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/167 ,  H01L29/161 ,  H01L21/02 ,  H01L29/08 ,  H01L29/24 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.

公开(公告)号：US08906802B2

公开(公告)日：2014-12-09

申请号：US13839284

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jeremy A. Wahl ,  Gerard M. Schmid ,  Richard A. Farrell ,  Chanro Park

IPC: H01L21/00 ,  G03C5/00 ,  H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76816

Abstract: One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with a DSA masking pattern, performing at least one process operation to form a patterned transfer masking layer having a transfer masking pattern comprised of a plurality of features that define a plurality of openings in the transfer masking layer, wherein the transfer masking pattern is the inverse of the DSA masking pattern, and performing at least one etching process through the patterned transfer masking layer on a layer of material to form a plurality of trench/via features in the layer of material.

Abstract translation: 本文公开的一种说明性方法包括以下步骤：执行定向自组装过程以形成DSA掩模层，执行至少一个处理操作以去除DSA掩模层的至少一个特征，从而限定图案化DSA 具有DSA掩模图案的掩模层，执行至少一个处理操作以形成图案化的传输掩蔽层，其具有由在传送掩蔽层中限定多个开口的多个特征组成的传输掩蔽图案，其中传输掩蔽图案是 DSA掩模图案的反向，并且通过在材料层上的图案化转印掩模层进行至少一个蚀刻工艺以在材料层中形成多个沟槽/通孔特征。

公开(公告)号：US20140273469A1

公开(公告)日：2014-09-18

申请号：US13839284

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC

Inventor： Jeremy A. Wahl ,  Gerard M. Schmid ,  Richard A. Farrell ,  Chanro Park

IPC: H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76816

Abstract: One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with a DSA masking pattern, performing at least one process operation to form a patterned transfer masking layer having a transfer masking pattern comprised of a plurality of features that define a plurality of openings in the transfer masking layer, wherein the transfer masking pattern is the inverse of the DSA masking pattern, and performing at least one etching process through the patterned transfer masking layer on a layer of material to form a plurality of trench/via features in the layer of material.

Abstract translation: 本文公开的一种说明性方法包括以下步骤：执行定向自组装过程以形成DSA掩模层，执行至少一个处理操作以去除DSA掩模层的至少一个特征，从而限定图案化DSA 具有DSA掩模图案的掩模层，执行至少一个处理操作以形成图案化的传输掩蔽层，其具有由在传送掩蔽层中限定多个开口的多个特征组成的传输掩蔽图案，其中传输掩蔽图案是 DSA掩模图案的反向，并且通过在材料层上的图案化转印掩模层进行至少一个蚀刻工艺以在材料层中形成多个沟槽/通孔特征。