公开(公告)号：US10388617B2

公开(公告)日：2019-08-20

申请号：US15793130

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Ronald Gene Filippi, Jr.

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/308 ,  H01L21/60

Abstract: The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.

公开(公告)号：US10325862B2

公开(公告)日：2019-06-18

申请号：US15657666

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

公开(公告)号：US10297546B2

公开(公告)日：2019-05-21

申请号：US15652594

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Erdem Kaltalioglu ,  Ronald G. Filippi, Jr. ,  Ping-Chuan Wang ,  Cathryn Christiansen

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/308 ,  H01L21/3065 ,  H01L23/522 ,  H01L21/306

Abstract: Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.

公开(公告)号：US20180261538A1

公开(公告)日：2018-09-13

申请号：US15976300

申请日：2018-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Atsushi Ogino

IPC: H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/28 ,  H01L21/283 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/48 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53295

Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.

公开(公告)号：US20180047648A1

公开(公告)日：2018-02-15

申请号：US15237066

申请日：2016-08-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhuojie Wu ,  Erdem Kaltalioglu

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L22/14 ,  H01L22/32 ,  H01L23/585 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3512

Abstract: A sensor for an integrated circuit (IC) structure is disclosed. The sensor includes a sensor layer in a layer of the IC structure, the sensor layer including: a first conductive structure disposed proximate a perimeter of the IC structure; and a second conductive structure disposed parallel to the first conductive structure and proximate the perimeter of the IC structure. The sensor also includes a set of interdigitating conductive elements including a first plurality of conductive elements electrically coupled to the first conductive structure interdigitating with a second plurality of conductive elements electrically coupled to the second conductive structure.