公开(公告)号：US09620587B2

公开(公告)日：2017-04-11

申请号：US14871181

申请日：2015-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L29/417 ,  H01L29/45 ,  H01L29/861 ,  H01L29/866

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

公开(公告)号：US09601486B2

公开(公告)日：2017-03-21

申请号：US15156750

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu ,  Anil Kumar

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L27/027 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

公开(公告)号：US09385527B2

公开(公告)日：2016-07-05

申请号：US14682910

申请日：2015-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manjunatha Govinda Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/04

CPC classification number: H02H9/046

Abstract: A circuit for electrostatic discharge (ESD) protection is disclosed. The circuit includes multiple transistors that are selectively turned on during an ESD event. An ESD sense circuit detects an ESD event and asserts signals to activate an ESD protection circuit which closes multiple protection transistors to dissipate current during the ESD event. During normal operation of the circuit, the signals are de-asserted, disabling the ESD protection circuit.

公开(公告)号：US09343590B2

公开(公告)日：2016-05-17

申请号：US14450887

申请日：2014-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu ,  Anil Kumar ,  Ruchil Kumar Jain

IPC: H01L29/861 ,  H01L29/06 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L29/0684 ,  H01L29/66128

Abstract: An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.

Abstract translation: 提供ESD器件用于保护电路免受静电放电，并且包括具有阳极和阴极的平面二极管。 阳极电耦合到电路的信号路径，并且阴极电耦合到电路的地。 ESD装置被配置为在电路的正常操作期间关闭并且响应于信号路径上的静电放电而导通。 器件中的两个耗尽区由隔离阱隔开。 响应于静电放电，耗尽区域调制（例如，加宽和合并），提供用于放电到电路接地的路径。

公开(公告)号：US10790276B2

公开(公告)日：2020-09-29

申请号：US16147303

申请日：2018-09-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L29/417 ,  H01L23/535 ,  H01L21/768 ,  G05B19/4097

Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

公开(公告)号：US10373946B2

公开(公告)日：2019-08-06

申请号：US16038532

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/74 ,  H01L29/861 ,  H01L29/06

Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a p-type substrate; a silicon-controlled rectifier (SCR) over the p-type substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode including a gate in the n-well region, the Schottky diode positioned to mitigate electrostatic discharge (ESD) across the negatively charged fin and the n-well region in response to application of a forward voltage across the gate.

公开(公告)号：US10083952B2

公开(公告)日：2018-09-25

申请号：US15423006

申请日：2017-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L29/74 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L29/0649 ,  H01L29/742 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/861

Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode spanning between the p-well region and the n-well region, the Schottky diode for controlling electrostatic discharge (ESD) across the negatively charged fin and the n-well region.

公开(公告)号：US20170309615A1

公开(公告)日：2017-10-26

申请号：US15134942

申请日：2016-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L23/535 ,  G05B19/4097 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L27/0288 ,  G05B19/4097 ,  G05B2219/45031 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/4175

Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

公开(公告)号：US20160322345A1

公开(公告)日：2016-11-03

申请号：US14699134

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Chien-Hsin Lee ,  Xiangxiang Lu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L27/0266 ,  H01L27/0292 ,  H01L27/088 ,  H01L29/0619

Abstract: An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction and a plurality of source/drain diffusion areas that extend parallel to one another in a second direction perpendicular to the first direction. Each source/drain diffusion area comprises a plurality of source/drain areas disposed between respective ones of the plurality of transistor gates. The ESD protection transistor device further includes a source contact positioned over each source area of the plurality of source areas and a drain contact positioned over each drain area of the plurality of drain areas. With respect to each source/drain diffusion area of the plurality of source/drain diffusion areas, the source contacts are offset from the drain contacts with respect to the first direction.

Abstract translation: 静电放电（ESD）保护晶体管器件包括在第一方向上彼此平行延伸的多个晶体管栅极和沿垂直于第一方向的第二方向彼此平行延伸的多个源极/漏极扩散区域 方向。 每个源极/漏极扩散区域包括设置在多个晶体管栅极中的相应的晶体管栅极之间的多个源极/漏极区域。 ESD保护晶体管器件还包括位于多个源极区域的每个源极区域上的源极接触点和位于多个漏极区域的每个漏极区域上的漏极接触点。 对于多个源极/漏极扩散区域的每个源极/漏极扩散区域，源极触点相对于第一方向从漏极触点偏移。

公开(公告)号：US09455316B2

公开(公告)日：2016-09-27

申请号：US14871289

申请日：2015-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan

IPC: H01L29/06 ,  H01L27/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/417 ,  H01L29/45 ,  H01L29/861 ,  H01L29/866

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.