公开(公告)号：US09576952B2

公开(公告)日：2017-02-21

申请号：US14188778

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj Joshi ,  Manfred Eller ,  Richard J. Carter ,  Srikanth Balaji Samavedam

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/0924

Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

Abstract translation: 提供集成电路和制造方法。 集成电路包括：设置在衬底结构上的变化的栅极结构，所述变化的栅极结构包括在衬底结构的第一区域中的第一栅极堆叠，以及在衬底结构的第二区域中的第二栅极堆叠; 所述第一区域中的第一场效应晶体管，所述第一场效应晶体管包括所述第一栅极叠层并具有第一阈值电压; 以及第二区域中的第二场效应晶体管，所述第二场效应晶体管包括所述第二栅极堆叠并且具有第二阈值电压，其中所述第一阈值电压不同于所述第二阈值电压。 所述方法包括提供变化的栅极结构，所述提供包括：具有不同厚度（es）的不同栅极结构的尺寸层。

公开(公告)号：US20160035630A1

公开(公告)日：2016-02-04

申请号：US14882640

申请日：2015-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

Abstract: One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.

Abstract translation: 本文公开的一种说明性方法包括执行第一多个外延沉积工艺，以在掩蔽P活性区域的同时，选择性地在N活性区域上方形成第一多个半导体材料，进行第二多个外延沉积工艺以形成第二多个 半导体材料选择性地在P有源区上方，同时掩蔽N有源区，在N-有源区中和上方形成N型晶体管，并在P-活性区中和上方形成P型晶体管。

公开(公告)号：US20150364426A1

公开(公告)日：2015-12-17

申请号：US14303714

申请日：2014-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti ,  Anurag Mittal ,  Manfred Eller

IPC: H01L23/538 ,  H01L23/66 ,  H01L29/06 ,  H01L27/06 ,  H01L29/94 ,  H01L27/08

CPC classification number: H01L27/0629 ,  H01L27/0805 ,  H01L29/94

Abstract: Embodiments of the present invention provide an improved decoupling capacitor structure. A contact region is disposed over a source/drain region of the decoupling capacitor structure. Each contact region is formed as a plurality of segments, wherein an inter-segment gap separates a segment of the plurality of segments from an adjacent segment of the plurality of segments. Embodiments may include multiple contact regions between two gate regions. Arrays of decoupling capacitors may arranged as an alternating “checkerboard” pattern of P-well and N-well structures, and may be oriented at a diagonal angle to a metallization layer to facilitate connections of multiple decoupling capacitors within the array.

Abstract translation: 本发明的实施例提供了一种改进的去耦电容器结构。 接触区域设置在去耦电容器结构的源极/漏极区域上。 每个接触区域形成为多个段，其中段间间隙将多个段中的段与多个段的相邻段分离。 实施例可以包括两个栅极区域之间的多个接触区域。 去耦电容器的阵列可以被布置为P阱和N阱结构的交替“棋盘”图案，并且可以以与金属化层对角的角度定向，以便于阵列内的多个去耦电容器的连接。

公开(公告)号：US20140227845A1

公开(公告)日：2014-08-14

申请号：US13766922

申请日：2013-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanxiang Liu ,  Manfred Eller ,  Johannes van Meer

IPC: H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823418

Abstract: One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second N-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material. In some cases, the capping material layer may be formed of a material having a Young's modulus of at least 180 GPa.

Abstract translation: 本文公开的一种说明性方法涉及形成由分别形成在第一和第二活性区域中和第二活性区域上的第一和第二N型晶体管组成的集成电路产品。 该方法通常涉及对第一和第二有源区域执行公共阈值电压调整离子注入工艺，形成第一和第二晶体管，执行非晶离子注入工艺以在第一有源区域中选择性地形成非晶材料区域，但不在第 第二有源区，在执行非晶化离子注入工艺之后，在第一和第二晶体管上方形成覆盖材料层，并执行重结晶退火工艺，以将非晶材料区域的至少一部分转化为结晶材料。 在一些情况下，封盖材料层可以由杨氏模量为至少180GPa的材料形成。

公开(公告)号：US10424584B2

公开(公告)日：2019-09-24

申请号：US16186781

申请日：2018-11-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088

Abstract: A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.

公开(公告)号：US10243059B2

公开(公告)日：2019-03-26

申请号：US15994614

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srikanth Balaji Samavedan ,  Manfred Eller ,  Min-hwa Chi ,  Hui Zang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/308

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.

公开(公告)号：US20180366461A1

公开(公告)日：2018-12-20

申请号：US15627835

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Haiting Wang ,  Daniel Jaeger

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0207 ,  H01L28/20 ,  H01L28/24 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the gates comprising a gate structure and a gate cap, forming a conductive resistor structure between the first and second adjacent gates, the conductive resistor structure having an uppermost surface that is positioned at a level that is below a level of an uppermost surface of the gate caps of the first and second adjacent gates, and forming first and second separate conductive resistor contact structures, each of which is conductively coupled to the conductive resistor structure.

公开(公告)号：US09799661B1

公开(公告)日：2017-10-24

申请号：US15397004

申请日：2017-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

IPC: H01L27/108 ,  H01L27/11 ,  H01L29/49 ,  H01L29/06 ,  H01L21/84 ,  H01L21/762 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L21/76283 ,  H01L29/0649

Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-down (PD1) transistor and a second pull-down (PD2) transistor. The at least one CBP facilitates biasing at least one of the PD1 and PD2 transistors during at least one of a read, write or standby operation of the structures.

公开(公告)号：US09734897B1

公开(公告)日：2017-08-15

申请号：US15397021

申请日：2017-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

IPC: G11C11/00 ,  G11C11/419 ,  H01L27/11 ,  H01L23/522 ,  H01L21/762 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pass gate (PG1) transistor and a second pass gate (PG2) transistor. The at least one CBP facilitates biasing of at least one the PG1 and PG2 transistors during at least one of a read, write or standby operation of the structures.

公开(公告)号：US09543297B1

公开(公告)日：2017-01-10

申请号：US14869397

申请日：2015-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Konstantin G. Korablev ,  Shesh Mani Pandey ,  Manfred Eller

IPC: H01L21/82 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/1083 ,  H01L29/66795

Abstract: A method of forming fins and the resulting fin-shaped field effect transistors (finFET) are provided. Embodiments include forming silicon (Si) fins over a substrate; forming a first metal over each of the Si fins; forming an isolation material over the first metal; removing an upper portion of the isolation material to expose and upper portion of the first metal; removing the upper portion of the first metal to expose an upper portion of each Si fin; removing the isolation material after removing the upper portion of the first metal; and forming a second metal over the first metal and the upper portion of the Si fins.

Abstract translation: 提供了一种形成翅片的方法和所得的鳍状场效应晶体管（finFET）。 实施例包括在衬底上形成硅（Si）鳍; 在每个Si散热片上形成第一金属; 在所述第一金属上形成隔离材料; 去除所述隔离材料的上部以暴露所述第一金属的上部; 去除第一金属的上部以暴露每个Si散热片的上部; 在去除第一金属的上部之后去除隔离材料; 以及在所述第一金属和所述Si翅片的上部上形成第二金属。