公开(公告)号：US10707206B2

公开(公告)日：2020-07-07

申请号：US16194691

申请日：2018-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L27/08 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311

Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.

公开(公告)号：US10699942B2

公开(公告)日：2020-06-30

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US20200168731A1

公开(公告)日：2020-05-28

申请号：US16776807

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L29/08

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

公开(公告)号：US20200168504A1

公开(公告)日：2020-05-28

申请号：US16778884

申请日：2020-01-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Ruilong Xie ,  Mark Raymond

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417

Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.

公开(公告)号：US10665586B2

公开(公告)日：2020-05-26

申请号：US15708911

申请日：2017-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Cheng Chi

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L29/08 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/285 ,  H01L21/8234 ,  H01L21/311

Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

公开(公告)号：US20200161296A1

公开(公告)日：2020-05-21

申请号：US16194691

申请日：2018-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.

公开(公告)号：US10658243B2

公开(公告)日：2020-05-19

申请号：US16002385

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Daniel Chanemougame ,  Steven R. Soss ,  Steven J. Bentley ,  Chanro Park

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L29/51

Abstract: The present disclosure relates to methods for forming replacement metal gate (RMG) structures and related structures. A method may include: forming a portion of sacrificial material around each fin of a set of adjacent fins; forming a first dielectric region between the portions of sacrificial material; forming a second dielectric region on the first dielectric region; forming an upper source/drain region from an upper portion of each fin; removing only the second dielectric region and the sacrificial material; and forming a work function metal (WFM) in place of the second dielectric region and the sacrificial material. The semiconductor structure may include gate structures surrounding adjacent fins; a first dielectric region between the gate structures; a second dielectric region above the first dielectric region and between the gate structures; and a liner between the first dielectric region and the gate structures such that the second dielectric region directly contacts the gate structures.

公开(公告)号：US20200152504A1

公开(公告)日：2020-05-14

申请号：US16185799

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/49

Abstract: Methods of forming a field-effect transistor and structures for a field effect-transistor. A sidewall spacer is formed adjacent to a sidewall of a gate structure of the field-effect transistor and a dielectric cap is formed over the gate structure and the sidewall spacer. A cut is formed that extends through the dielectric cap, the gate structure, and the sidewall spacer. After forming the cut, the sidewall spacer is removed from beneath the dielectric cap to define a cavity, and a dielectric material is deposited in the cut and in the cavity. The dielectric material encapsulates a portion of the cavity to define an airgap spacer.

公开(公告)号：US10651284B2

公开(公告)日：2020-05-12

申请号：US15791650

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

公开(公告)号：US10607893B2

公开(公告)日：2020-03-31

申请号：US15898569

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions; contacts connecting to the source and drain regions; contacts connecting to the gate structures which are offset from the contacts connecting to the source and drain regions; and interconnect structures in electrical contact with the contacts of the gate structures and the contacts of the source and drain regions.