公开(公告)号：US20160217832A1

公开(公告)日：2016-07-28

申请号：US14604009

申请日：2015-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Jayaraman ,  Thejas Kempanna ,  Toshiaki Kirihata ,  Ramesh Raghavan ,  Krishnan S. Rengarajan ,  Rajesh R. Tummuru

IPC: G11C7/06 ,  G11C7/08

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C11/401 ,  G11C11/4091 ,  G11C2211/4013

Abstract: A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The memory cell includes a pair of a first transistor and a second transistor providing a differential signal output. The first transistor of the memory cell couples a first circuit leg having a first current source load transistor and the second transistor couples a second circuit leg having a second current source load transistor. A programmed value is represented by a voltage threshold shift in one of the first or second transistors. A feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.

Abstract translation: 一种操作双晶体管单比特多时间可编程存储器单元以提供小信号的高增益感测方案的系统和方法。 存储单元包括一对第一晶体管和提供差分信号输出的第二晶体管。 存储单元的第一晶体管耦合具有第一电流源负载晶体管的第一电路支路，而第二晶体管耦合具有第二电流源负载晶体管的第二电路支路。 编程值由第一或第二晶体管之一中的电压阈值偏移来表示。 反馈电路接收差分信号的第一信号或第二信号中的一个，并且响应地产生反馈信号，该反馈信号被同时施加以偏置每个第一和第二电路腿中的每个电流源负载晶体管，以放大 差分信号输出之间的电压差。

公开(公告)号：US09355739B2

公开(公告)日：2016-05-31

申请号：US14084644

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pamela Castalino ,  Toshiaki Kirihata ,  Derek H. Leu

IPC: G11C11/56 ,  G11C16/04 ,  G11C17/18 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C17/18 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices. The bitline circuits having mode and bank access dependent bitline circuit further enables a single device memory array, by using two arrays, wherein said one of the array is used for reference to the other array using an open bitline architecture.

Abstract translation: 嵌入式多时间只读存储器的位线电路，包括耦合到每行中的多个字线，每列中的位线和源极线的多个NMOS存储器单元。 更具体地，位线电路通过模式相关的位线下拉电路来控制目标NMOS存储器阵列的电荷陷阱行为，从而将位线强烈地放电到GND，以在编程模式下有效地捕获电荷，并将位线弱化 GND产生位线电压以检测电荷陷阱状态。 模式相关电路通过使用至少两个NMOS来切换器件强度，使用读取模式下的脉冲栅极控制或使用模拟电压来限制位线电流来实现。 所提出的方法还包括保护装置，允许使用薄氧化物装置的所有位线控制电路。 具有模式和与银行接入相关的位线电路的位线电路还通过使用两个阵列使单个设备存储器阵列进一步启用，其中阵列中的所述一个使用打开的位线架构用于引用另一阵列。

公开(公告)号：US09859177B2

公开(公告)日：2018-01-02

申请号：US15062484

申请日：2016-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Janakiraman Viraraghavan ,  Ramesh Raghavan ,  Balaji Jayaraman ,  Thejas Kempanna ,  Rajesh R. Tummuru ,  Toshiaki Kirihata

IPC: G11C7/00 ,  H01L21/66 ,  H01L27/115 ,  H01L27/105 ,  H01L49/02

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L22/20 ,  H01L22/22 ,  H01L27/1052 ,  H01L27/115 ,  H01L28/40

Abstract: Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.

公开(公告)号：US09786333B2

公开(公告)日：2017-10-10

申请号：US15478820

申请日：2017-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Janakiraman Viraraghavan ,  Thejas Kempanna ,  Rajesh Reddy Tummuru ,  Toshiaki Kirihata

IPC: G11C11/56 ,  G11C5/06 ,  G11C5/14 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C5/06 ,  G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/18 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2211/4013

Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.

公开(公告)号：US20170206938A1

公开(公告)日：2017-07-20

申请号：US15478820

申请日：2017-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Janakiraman Viraraghavan ,  Thejas Kempanna ,  Rajesh Reddy Tummuru ,  Toshiaki Kirihata

IPC: G11C5/06 ,  G11C7/06 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C5/06 ,  G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/18 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2211/4013

Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.