公开(公告)号：US20150364378A1

公开(公告)日：2015-12-17

申请号：US14301748

申请日：2014-06-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Min Gyu Sung

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/28

CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/0653

Abstract: One method disclosed herein includes forming an opening in a layer of material so as to expose the source/drain regions of a transistor and a first portion of a gate cap layer positioned above an active region, reducing the thickness of a portion of the gate cap layer positioned above the isolation region, defining separate initial source/drain contacts positioned on opposite sides of the gate structure, performing a common etching process sequence to define a gate contact opening that extends through the reduced-thickness portion of the gate cap layer and a plurality of separate source/drain contact openings in the layer of insulating material, and forming a conductive gate contact structure and conductive source/drain contact structures.

Abstract translation: 本文公开的一种方法包括在材料层中形成开口以暴露晶体管的源极/漏极区域和位于有源区域上方的栅极覆盖层的第一部分，从而减小栅极帽部分的厚度 位于隔离区域上方的层，限定位于栅极结构的相对侧上的单独的初始源极/漏极触点，执行公共蚀刻工艺序列以限定延伸穿过栅极盖层的厚度减小的部分的栅极接触开口，以及 绝缘材料层中的多个独立的源极/漏极接触开口，以及形成导电栅极接触结构和导电源极/漏极接触结构。

公开(公告)号：US20150340497A1

公开(公告)日：2015-11-26

申请号：US14283636

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Naim Moumen ,  Chanro Park ,  William J. Taylor, JR.

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer.

Abstract translation: 所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，执行外延沉积工艺以在器件的源极/漏极区域中的有源区上形成外延半导体材料，进行蚀刻 处理外延半导体材料以去除外延半导体材料的一部分，以便限定外延半导体材料中的至少一个外延凹部，在外延半导体材料的上表面上形成金属硅化物层，并且在至少一个 epi凹槽，并且形成导电耦合到金属硅化物层的导电结构。

公开(公告)号：US20140225168A1

公开(公告)日：2014-08-14

申请号：US13764115

申请日：2013-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel T. Pham ,  Werner Juengling ,  William J. Taylor, JR. ,  Robert Miller

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.

Abstract translation: 一种方法包括形成第一和第二间隔开的沟槽，其至少部分延伸到限定用于器件的鳍结构的半导体衬底中，形成在第一沟槽中具有第一类型应力的应力诱导材料，形成第二应力诱导 第二沟槽中的材料，第二应力诱导材料具有不同于第一类型应力的第二应力，以及围绕鳍结构的一部分形成栅极结构。 一个器件包括在半导体衬底中限定用于器件的鳍片的至少一部分的第一和第二间隔开的沟槽，在第一沟槽中具有第一类型应力的应力诱导材料，在第一沟槽中的第二应力诱导材料 第二沟槽，第二应力诱导材料具有与第一应力不同的第二应力，以及围绕鳍结构的一部分的栅极结构。

公开(公告)号：US20170018459A1

公开(公告)日：2017-01-19

申请号：US15277732

申请日：2016-09-27

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Sukwon Hong ,  William J. Taylor, JR.

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

Abstract translation: 互连结构包括在半导体衬底的上表面上的绝缘体堆叠。 绝缘体堆叠包括具有嵌入其中的至少一个半导体器件的第一绝缘体层和插入在第一绝缘体层和第二绝缘体层之间的蚀刻停止层。 至少一个导电局部接触件延伸穿过第二绝缘体层，蚀刻停止层和与第一半导体器件接触的第一绝缘体层中的每一个。 所述互连结构还包括设置在所述蚀刻停止层上并抵靠所述至少一个导电性局部接触的至少一个第一层接触元件。

公开(公告)号：US20150340452A1

公开(公告)日：2015-11-26

申请号：US14817628

申请日：2015-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-Han Kim ,  William J. Taylor, JR.

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface of the recess and forming at least one source/drain contact structure for each of the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure. The upper surface of each of the buried fin contact structures is positioned below an upper surface of the raised isolation structure and an outer perimeter surface of each of the buried fin contact structures contacts at least a portion of an interior perimeter surface of the recess.

Abstract translation: 一种方法包括形成具有在衬底上方的凹陷的凸起的隔离结构，在鳍的上方形成栅极结构，在凹槽内形成多个间隔开的隐埋翅片接触结构，其具有外周表面，该外周表面接触至少部分 凹陷的内周边表面，并形成用于每个埋入鳍接触结构的至少一个源极/漏极接触结构。 一个装置包括位于栅极结构的相对侧上的凸起的隔离结构中的凹部内的多个间隔开的埋入式翅片接触结构。 每个埋入式翅片接触结构的上表面位于凸起隔离结构的上表面的下方，并且每个埋入式翅片接触结构的外周表面与凹部的内周边表面的至少一部分接触。

公开(公告)号：US20150060960A1

公开(公告)日：2015-03-05

申请号：US14017781

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Ryan Ryoung-Han Kim ,  William J. Taylor, JR.

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface of the recess and forming at least one source/drain contact structure for each of the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure. The upper surface of each of the buried fin contact structures is positioned below an upper surface of the raised isolation structure and an outer perimeter surface of each of the buried fin contact structures contacts at least a portion of an interior perimeter surface of the recess.

Abstract translation: 一种方法包括形成具有在衬底上方的凹陷的凸起的隔离结构，在鳍的上方形成栅极结构，在凹槽内形成多个间隔开的隐埋翅片接触结构，其具有外周表面，该外周表面接触至少部分 凹陷的内周边表面，并形成用于每个埋入鳍接触结构的至少一个源极/漏极接触结构。 一个装置包括位于栅极结构的相对侧上的凸起的隔离结构中的凹部内的多个间隔开的埋入式翅片接触结构。 每个埋入式翅片接触结构的上表面位于凸起隔离结构的上表面的下方，并且每个埋入式翅片接触结构的外周表面与凹部的内周边表面的至少一部分接触。

公开(公告)号：US20150044855A1

公开(公告)日：2015-02-12

申请号：US14524076

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  William J. Taylor, JR.

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.

Abstract translation: 这里公开了在FinFET和其它半导体器件上形成间隔物的各种方法。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其限定鳍片，在沟槽中形成绝缘材料的第一层，所述第一绝缘材料层覆盖鳍片的下部，但暴露鳍片的上部 并且在所述暴露的所述翅片的上部上形成第二绝缘材料层。 所述方法还包括在所述鳍的上表面和所述沟槽的底部中选择性地形成电介质材料，在所述器件的栅极结构之上和在所述鳍上方和所述沟槽中的所述电介质材料之上沉积间隔物材料层， 以及对所述隔离层材料层进行蚀刻处理以限定邻近所述栅极结构定位的侧壁间隔物。

公开(公告)号：US20140256064A1

公开(公告)日：2014-09-11

申请号：US13789966

申请日：2013-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： William J. Taylor, JR. ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/02

CPC classification number: H01L21/31155 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828

Abstract: One illustrative method disclosed herein includes providing a layer of a carbon-containing insulating material having a nominal carbon concentration, performing at least one process operation on the carbon-containing insulating material that results in the formation of a reduced-carbon-concentration region in the layer of carbon-containing insulating material, wherein the reduced-carbon-concentration region has a carbon concentration that is less than the nominal carbon concentration, performing a carbon-introduction process operation to introduce carbon atoms into at least the reduced-carbon-concentration region and thereby define a carbon-enhanced region having a carbon concentration that is greater than the carbon concentration of the reduced-carbon-concentration region and, after introducing the carbon atoms, performing a heating process on at least the carbon-enhanced region.

Abstract translation: 本文公开的一种说明性方法包括提供具有标称碳浓度的含碳绝缘材料的层，对含碳绝缘材料进行至少一个工艺操作，导致在所述含碳绝缘材料中形成还原碳浓度区域 含碳绝缘材料层，其中所述还原碳浓度区域的碳浓度小于标称碳浓度，进行碳引入工艺操作以将碳原子引入至少所述还原碳浓度区域 由此确定碳浓度大于还原碳浓度区域的碳浓度的碳增强区域，并且在引入碳原子之后，至少对碳增强区域进行加热处理。