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    FINFET SEMICONDUCTOR DEVICES WITH IMPROVED SOURCE/DRAIN RESISTANCE
    2.
    发明申请
    FINFET SEMICONDUCTOR DEVICES WITH IMPROVED SOURCE/DRAIN RESISTANCE 审中-公开
    具有改进的源/漏电阻的FINFET半导体器件

    公开(公告)号：US20150349069A1

    公开(公告)日：2015-12-03

    申请号：US14822167

    申请日：2015-08-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Mark Raymond ,  Robert Miller

    IPC: H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/51

    CPC classification number: H01L29/41725 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

    Abstract: A FinFET device includes a plurality of spaced-apart trenches in a semiconducting substrate, the plurality of spaced-apart trenches at least partially defining a fin for the FinFET device, wherein the fin comprises a first semiconductor material. A first layer of insulating material is positioned above a bottom surface of each of the plurality of spaced-apart trenches and an etch stop layer is positioned above an upper surface of the first layer of insulating material in each of the plurality of spaced-apart trenches. A metal silicide region is positioned on at least all sidewall surfaces of the fin that extend above the upper surface of the etch stop layer.

    Abstract translation: FinFET器件在半导体衬底中包括多个间隔开的沟槽，多个间隔开的沟槽至少部分地限定FinFET器件的鳍片，其中鳍片包括第一半导体材料。 第一层绝缘材料位于多个间隔开的沟槽中的每一个的底表面上方，并且在多个间隔开的沟槽中的每一个中位于第一绝缘材料层的上表面上方的蚀刻停止层 。 金属硅化物区域位于鳍片的至少所有侧壁表面上，其在蚀刻停止层的上表面上方延伸。

    Silicide protection during contact metallization and resulting semiconductor structures
    3.
    发明授权
    Silicide protection during contact metallization and resulting semiconductor structures 有权
    接触金属化期间的硅化物保护和由此产生的半导体结构

    公开(公告)号：US09111907B2

    公开(公告)日：2015-08-18

    申请号：US14146399

    申请日：2014-01-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal K. Kamineni ,  Ruilong Xie ,  Robert Miller

    IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/417 ,  H01L21/285 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7851 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

    Abstract translation: 半导体晶体管具有在源极区域和漏极区域之间的半导体衬底，源极区域，漏极区域和沟道区域的结构。 在通道区域的上方设置有具有钨的顶部导电部分的金属栅极。 提供了源极区域和漏极区域上的第一氮化硅保护层和栅极区域上的第二氮化硅保护层。 第一氮化硅保护层和第二氮化硅保护层被配置为允许第一氮化硅保护层的穿通，同时防止蚀刻通过第二氮化硅保护层。 通过避免完全蚀刻栅极开口来保护源极和漏极硅化物，除非所用的蚀刻不会对硅化物造成伤害，或者在完全蚀刻用于栅极接触的栅极的开口之前产生硅化物和源极和漏极接触。

    METHODS OF FORMING A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE WITH A DUAL STRESS CHANNEL AND THE RESULTING DEVICE
    4.
    发明申请
    METHODS OF FORMING A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE WITH A DUAL STRESS CHANNEL AND THE RESULTING DEVICE 有权
    形成具有双应力通道和结果设备的三维半导体器件的方法

    公开(公告)号：US20140225168A1

    公开(公告)日：2014-08-14

    申请号：US13764115

    申请日：2013-02-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Daniel T. Pham ,  Werner Juengling ,  William J. Taylor, JR. ,  Robert Miller

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L29/7846 ,  H01L29/785

    Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.

    Abstract translation: 一种方法包括形成第一和第二间隔开的沟槽，其至少部分延伸到限定用于器件的鳍结构的半导体衬底中，形成在第一沟槽中具有第一类型应力的应力诱导材料，形成第二应力诱导 第二沟槽中的材料，第二应力诱导材料具有不同于第一类型应力的第二应力，以及围绕鳍结构的一部分形成栅极结构。 一个器件包括在半导体衬底中限定用于器件的鳍片的至少一部分的第一和第二间隔开的沟槽，在第一沟槽中具有第一类型应力的应力诱导材料，在第一沟槽中的第二应力诱导材料 第二沟槽，第二应力诱导材料具有与第一应力不同的第二应力，以及围绕鳍结构的一部分的栅极结构。

    SILICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES
    6.
    发明申请
    SILICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES 有权
    接触式金属化和半导体结构中的硅化物保护

    公开(公告)号：US20150187896A1

    公开(公告)日：2015-07-02

    申请号：US14146399

    申请日：2014-01-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal K. Kamineni ,  Ruilong Xie ,  Robert Miller

    IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285

    CPC classification number: H01L29/7851 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

    Abstract translation: 半导体晶体管具有在源极区域和漏极区域之间的半导体衬底，源极区域，漏极区域和沟道区域的结构。 在通道区域的上方设置有具有钨的顶部导电部分的金属栅极。 提供了源极区域和漏极区域上的第一氮化硅保护层和栅极区域上的第二氮化硅保护层。 第一氮化硅保护层和第二氮化硅保护层被配置为允许第一氮化硅保护层的穿通，同时防止蚀刻通过第二氮化硅保护层。 通过避免完全蚀刻栅极开口来保护源极和漏极硅化物，除非所用的蚀刻不会对硅化物造成伤害，或者在完全蚀刻用于栅极接触的栅极的开口之前产生硅化物和源极和漏极接触。

    Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
    7.
    发明授权
    Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device 有权
    用双应力通道形成三维半导体器件的方法和所得到的器件

    公开(公告)号：US08877588B2

    公开(公告)日：2014-11-04

    申请号：US13764115

    申请日：2013-02-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Daniel T. Pham ,  Werner Juengling ,  William J. Taylor, Jr. ,  Robert Miller

    IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/66795 ,  H01L29/7846 ,  H01L29/785

    Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.

    Abstract translation: 一种方法包括形成第一和第二间隔开的沟槽，其至少部分延伸到限定用于器件的鳍结构的半导体衬底中，形成在第一沟槽中具有第一类型应力的应力诱导材料，形成第二应力诱导 第二沟槽中的材料，第二应力诱导材料具有不同于第一类型应力的第二应力，以及围绕鳍结构的一部分形成栅极结构。 一个器件包括在半导体衬底中限定用于器件的鳍片的至少一部分的第一和第二间隔开的沟槽，在第一沟槽中具有第一类型应力的应力诱导材料，在第一沟槽中的第二应力诱导材料 第二沟槽，第二应力诱导材料具有与第一应力不同的第二应力，以及围绕鳍结构的一部分的栅极结构。

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