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    METHODS OF FORMING STRESSED FIN CHANNEL STRUCTURES FOR FINFET SEMICONDUCTOR DEVICES
    2.
    发明申请
    METHODS OF FORMING STRESSED FIN CHANNEL STRUCTURES FOR FINFET SEMICONDUCTOR DEVICES 有权
    为FINFET半导体器件形成应力FIN通道结构的方法

    公开(公告)号：US20150041906A1

    公开(公告)日：2015-02-12

    申请号：US13960200

    申请日：2013-08-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, JR.

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

    Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

    Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。

    SEMICONDUCTOR DEVICES WITH CONTACT STRUCTURES AND A GATE STRUCTURE POSITIONED IN TRENCHES FORMED IN A LAYER OF MATERIAL
    3.
    发明申请
    SEMICONDUCTOR DEVICES WITH CONTACT STRUCTURES AND A GATE STRUCTURE POSITIONED IN TRENCHES FORMED IN A LAYER OF MATERIAL 有权
    具有接触结构的半导体器件和位于材料层中形成的倾斜物中的门结构

    公开(公告)号：US20150279935A1

    公开(公告)日：2015-10-01

    申请号：US14242416

    申请日：2014-04-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Ryan Ryoung-Han Kim

    IPC: H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/51

    CPC classification number: H01L29/0847 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851

    Abstract: One illustrative device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material positioned above the substrate, a plurality of laterally spaced-apart source/drain trenches formed in the layer of material above the active region, a conductive source/drain contact structure formed within each of the source/drain trenches, a gate trench formed at least partially in the layer of material between the spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.

    Abstract translation: 本文公开的一个说明性器件尤其包括限定在半导体衬底中的有源区，位于衬底上方的材料层，形成在有源区上方的材料层中的多个横向间隔开的源极/漏极沟槽 形成在每个源极/漏极沟槽内的导电源极/漏极接触结构，至少部分地形成在材料层中的间隔开的源极/漏极沟槽之间的材料层中的栅极沟槽，其中层的部分 的材料保持位于源极/漏极沟槽和栅极沟槽之间，位于栅极沟槽内的栅极结构以及位于栅极结构之上的栅极盖层。

    METHODS OF FORMING STRESSED LAYERS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
    4.
    发明申请
    METHODS OF FORMING STRESSED LAYERS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES 有权
    在FINFET半导体器件和结构器件上形成受压层的方法

    公开(公告)号：US20150076609A1

    公开(公告)日：2015-03-19

    申请号：US14030540

    申请日：2013-09-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Ryan Ryoung-han Kim ,  William J. Taylor, JR.

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7846 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess and forming a stress-inducing material layer above the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure, a stress-inducing material layer formed above the buried fin contact structures and a source/drain contact that extends through the stress-inducing material layer.

    Abstract translation: 一种方法包括形成具有在衬底上方的凹陷的凸起的隔离结构，在鳍的上方形成栅极结构，在凹槽内形成多个间隔开的隐埋翅片接触结构，并在埋入鳍接触件上方形成应力诱导材料层 结构。 一个装置包括位于栅极结构的相对侧上的凸起的隔离结构的凹部内的多个间隔开的埋入式翅片接触结构，形成在埋入式翅片接触结构上方的应力诱导材料层和源极/漏极接点， 延伸穿过应力诱导材料层。

    INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER
    5.
    发明申请
    INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER 有权
    互连结构，包括中间线（MOL）金属层局部互连在蚀刻停止层

    公开(公告)号：US20160379932A1

    公开(公告)日：2016-12-29

    申请号：US14753407

    申请日：2015-06-29

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Su Chen Fan ,  Sukwon Hong ,  William J. Taylor, JR.

    IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

    Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

    Abstract translation: 互连结构包括在半导体衬底的上表面上的绝缘体堆叠。 绝缘体堆叠包括具有嵌入其中的至少一个半导体器件的第一绝缘体层和插入在第一绝缘体层和第二绝缘体层之间的蚀刻停止层。 至少一个导电局部接触件延伸穿过第二绝缘体层，蚀刻停止层和与第一半导体器件接触的第一绝缘体层中的每一个。 所述互连结构还包括设置在所述蚀刻停止层上并抵靠所述至少一个导电性局部接触的至少一个第一层接触元件。

    SEMICONDUCTOR DEVICES WITH A LAYER OF MATERIAL HAVING A PLURALITY OF SOURCE/DRAIN TRENCHES
    6.
    发明申请
    SEMICONDUCTOR DEVICES WITH A LAYER OF MATERIAL HAVING A PLURALITY OF SOURCE/DRAIN TRENCHES 审中-公开
    具有多种源/排水沟的材料层的半导体器件

    公开(公告)号：US20150349053A1

    公开(公告)日：2015-12-03

    申请号：US14823226

    申请日：2015-08-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Ryan Ryoung-Han Kim

    IPC: H01L29/06 ,  H01L29/51 ,  H01L29/08 ,  H01L29/78

    CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

    Abstract: One device disclosed herein includes an active region defined in a semiconductor substrate, a layer of material positioned above the semiconductor substrate, first and second laterally spaced-apart source/drain trenches defined in the layer of material above the active region, first and second conductive source/drain contact structures positioned within the first and second laterally spaced-apart source/drain trenches, respectively, a gate trench formed at least partially in the layer of material between the first and second laterally spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the first and second laterally spaced-apart source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.

    Abstract translation: 本文公开的一种器件包括限定在半导体衬底中的有源区，位于半导体衬底上方的材料层，在有源区上方的材料层中限定的第一和第二横向间隔开的源极/漏极沟槽，第一和第二导电 源极/漏极接触结构分别位于第一和第二横向间隔开的源极/漏极沟槽内，栅极沟槽至少部分地形成在层中的第一和第二横向间隔开的源极/漏极沟槽之间的材料层中 的材料层，其中材料层的部分保持位于第一和第二横向间隔开的源极/漏极沟槽和栅极沟槽之间，位于栅极沟槽内的栅极结构以及位于栅极结构上方的栅极盖层。

    METHODS OF FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
    10.
    发明申请
    METHODS OF FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES 有权
    形成半导体器件和结果器件的接触结构的方法

    公开(公告)号：US20160049332A1

    公开(公告)日：2016-02-18

    申请号：US14457708

    申请日：2014-08-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Vimal Kamineni ,  William J. Taylor, JR.

    IPC: H01L21/768 ,  H01L23/535

    CPC classification number: H01L29/4975 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41758 ,  H01L29/78 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One method disclosed herein includes, among other things, a method of forming a contact structure to a source/drain region of a transistor device. The transistor device includes a gate structure and a gate cap layer positioned above the gate structure. The method includes forming an extended-height epi contact structure that is conductively coupled to the source/drain region. The extended-height epi contact structure includes an upper surface that is positioned at a height level that is above a height level of an upper surface of the gate cap layer. The method further includes performing an etching process to trim at least a lateral width of a portion of the extended-height epi contact structure, and, after performing the etching process, forming a metal silicide material on at least a portion of the trimmed extended-height epi contact structure and forming a conductive contact on the metal silicide material.

    Abstract translation: 本文公开的一种方法包括形成与晶体管器件的源极/漏极区域的接触结构的方法。 晶体管器件包括栅极结构和位于栅极结构上方的栅极帽层。 该方法包括形成导电耦合到源极/漏极区的扩展高度外延接触结构。 所述延伸高度外延接触结构包括位于所述栅极盖层的上表面的高度以上的高度水平处的上表面。 该方法还包括执行蚀刻工艺以修剪延伸高度外延接触结构的一部分的至少横向宽度，并且在执行蚀刻工艺之后，在修剪的延伸高度外延接触结构的至少一部分上形成金属硅化物材料， 高度epi接触结构，并在金属硅化物材料上形成导电接触。

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