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    FIN-TYPE TRANSISTORS WITH SPACERS ON THE GATES
    11.
    发明申请
    FIN-TYPE TRANSISTORS WITH SPACERS ON THE GATES 审中-公开

    公开(公告)号：US20190280105A1

    公开(公告)日：2019-09-12

    申请号：US15916323

    申请日：2018-03-09

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Qun Gao ,  Jerome Ciavatti ,  Yi Qi ,  Wei Hong ,  Yongjun Shi ,  Jae Gon Lee ,  Chun Yu Wong

    IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238

    Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

    Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
    14.
    发明授权
    Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via 有权

    公开(公告)号：US09761481B2

    公开(公告)日：2017-09-12

    申请号：US13748159

    申请日：2013-01-23

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Chun Yu Wong ,  Sarasvathi Thangaraju ,  Percival Rayo

    IPC: H01L21/768 ,  H01L23/528

    CPC classification number: H01L21/76807 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor substrate. At least one through-semiconductor via is formed in the semiconductor substrate and an interlayer dielectric layer is formed overlying the at least one through-semiconductor via and the plurality of semiconductor devices. A first pattern is etched in the interlayer dielectric layer over the at least one through-semiconductor via, and a second pattern different from the first pattern is etched in the interlayer dielectric layer over the same through-semiconductor via as the first pattern. At least one interconnect via is embedded within the interlayer dielectric layer, in electrical communication with one of the at least one through-semiconductor vias. A metal-containing material is deposited in the first pattern and the second pattern to form a first metal layer in electrical communication with the at least one interconnect via.

    Fin field-effect transistor (FinFET) and method of production thereof
    17.
    发明授权
    Fin field-effect transistor (FinFET) and method of production thereof 有权

    公开(公告)号：US10418285B1

    公开(公告)日：2019-09-17

    申请号：US15993142

    申请日：2018-05-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hui Zang ,  Chun Yu Wong ,  Laertis Economikos

    IPC: H01L29/06 ,  H01L21/8234

    Abstract: Methods of forming a CT pillar with reduced width and increased distance from neighboring fins and the resulting devices are provided. Embodiments include providing a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins include Si; and forming a CT pillar including SiN between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.

    Methods of fabricating nanowire structures
    20.
    发明授权
    Methods of fabricating nanowire structures 有权
    制造纳米线结构的方法

    公开(公告)号：US09508795B2

    公开(公告)日：2016-11-29

    申请号：US14613983

    申请日：2015-02-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chun Yu Wong ,  Min-hwa Chi ,  Ashish Baraskar ,  Jagar Singh

    IPC: H01L21/20 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

    CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/31116 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/78696

    Abstract: Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.

    Abstract translation: 提出了用于制造纳米线结构的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括例如：提供衬底并在衬底上形成翅片，使得翅片具有包括一个或多个细长的第一侧壁突出部的第一侧壁和包括一个或多个细长的第二侧壁突出部的第二侧壁， 更细长的第二侧壁突起基本上与一个或多个细长的第一侧壁突起对准; 并且用细长的第一侧壁突起和细长的第二侧壁突起各向异性地蚀刻翅片以限定一个或多个纳米线。 可以选择蚀刻剂以沿着预定义的结晶平面（例如（111）晶面）选择性地蚀刻，以形成纳米线结构。

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