公开(公告)号：US10580857B2

公开(公告)日：2020-03-03

申请号：US16010694

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanzhen Wang ,  Xinyuan Dou ,  Hongliang Shen ,  Sipeng Gu

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.

公开(公告)号：US20190386100A1

公开(公告)日：2019-12-19

申请号：US16010694

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanzhen Wang ,  Xinyuan Dou ,  Hongliang Shen ,  Sipeng Gu

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.

公开(公告)号：US10324381B1

公开(公告)日：2019-06-18

申请号：US16159877

申请日：2018-10-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Erfeng Ding ,  Guoxiang Ning

IPC: G01B11/00 ,  G03F7/20 ,  H01L21/768 ,  H01L27/088 ,  G06F17/50

Abstract: A method to address overlay accuracy compensation using finFET cut isolation revisions is disclosed. For an integrated circuit (IC) layout including at least a portion of an active region including a plurality of gates extending over a plurality of fins, prior to optical proximity correction of the IC layout: the method determines a number of fins to be cut with same source/drain connection by a fin cut isolation opening, and determines a fin cut isolation pitch in the gate length direction of the plurality of gates. The method revises a size of a fin cut isolation opening in the IC layout based on a number of fins to be cut with same source/drain connection by the fin cut isolation opening and the fin cut isolation pitch in the gate length direction. The revision in size of the fin cut isolation compensates for overlay inaccuracy.

公开(公告)号：US09373535B2

公开(公告)日：2016-06-21

申请号：US14515628

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Zhenyu Hu ,  Jin Ping Liu

IPC: H01L21/62 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/76232 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6681

Abstract: Semiconductor devices and fabrication methods are provided having an isolation feature within a fin structure which, for instance, facilitates isolating circuit elements supported by the fin structure. The fabrication method includes, for instance, providing an isolation material disposed, in part, within the fin structure, the isolation material being formed to include a T-shaped isolation region and a first portion extending into the fin structure, and a second portion disposed over the first portion and extending above the fin structure.

Abstract translation: 提供半导体器件和制造方法，其具有翅片结构内的隔离特征，其例如有助于隔离由鳍结构支撑的电路元件。 制造方法包括例如提供部分地设置在鳍结构内的隔离材料，隔离材料被形成为包括T形隔离区域和延伸到翅片结构中的第一部分，并且第二部分设置在 在第一部分之上并且延伸到翅片结构之上。

公开(公告)号：US20160049468A1

公开(公告)日：2016-02-18

申请号：US14823319

申请日：2015-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Wanxun He ,  Hongliang Shen

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0646 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.

Abstract translation: 公开了一种集成电路产品，其包括限定第一，第二和第三鳍片的半导体衬底中的多个沟槽，其中散热片并排，并且其中第二鳍片位于第一和第三鳍片之间， 多个沟槽中的绝缘材料层，使得第一，第二和第三鳍片的期望高度位于绝缘材料层的上表面上方，限定在第二鳍片中的凹部，其至少部分地限定在第 所述绝缘材料层，在所述第二鳍片的凹陷部分上的空腔中的SDB隔离结构，其中所述SDB隔离结构具有位于所述绝缘材料层的上表面上方的上表面，以及用于 晶体管位于SDB隔离结构之上。

公开(公告)号：US20150333121A1

公开(公告)日：2015-11-19

申请号：US14810167

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US20150333062A1

公开(公告)日：2015-11-19

申请号：US14809216

申请日：2015-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： XUSHENG WU ,  Wanxun He ,  Hongliang Shen

IPC: H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

Abstract translation: 本发明的实施例提供了一种用于制造鳍式场效应晶体管（finFET）的改进方法。 牺牲区域形成在半导体衬底上。 间隔件邻近牺牲区域的两侧形成。 翅片基于间隔件形成。 将一组间隔物作为假间隔物处理，并且在翅片形成之前被除去，留下用于在最终半导体结构上形成翅片的另一组间隔件。 最终半导体结构上的所有鳍都由牺牲材料的一侧上的间隔物形成。 这减少了散热片的宽度变化。

公开(公告)号：US09171752B1

公开(公告)日：2015-10-27

申请号：US14457325

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Wanxun He ,  Hongliang Shen

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0646 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: One illustrative method disclosed herein includes, among other things, forming first, second and third fins that are arranged side-by-side, forming a recessed layer of insulating material in a plurality of trenches, after recessing the layer of insulating material, masking the first and second fins while exposing a portion of the axial length of the second fin, removing the exposed portion of the second fin so as to thereby define a cavity in the recessed layer of insulating material, forming an SDB isolation structure in the cavity, wherein the SDB isolation structure has an upper surface that is positioned above the recessed upper surface of the recessed layer of insulating material, removing the masking layer, and forming a gate structure for a transistor above the SDB isolation structure.

Abstract translation: 本文公开的一种说明性方法包括形成并排布置的第一，第二和第三鳍片，在凹陷绝缘材料层之后，在多个沟槽中形成绝缘材料的凹陷层，掩蔽 第一和第二鳍片，同时暴露第二鳍片的轴向长度的一部分，去除第二鳍片的暴露部分，从而在绝缘材料的凹陷层中限定空腔，在空腔中形成SDB隔离结构，其中 SDB隔离结构具有位于绝缘材料的凹陷层的凹陷的上表面上方的上表面，去除掩模层，并且在SDB隔离结构之上形成用于晶体管的栅极结构。

公开(公告)号：US20150076653A1

公开(公告)日：2015-03-19

申请号：US14028724

申请日：2013-09-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Richard J. Carter ,  Hongliang Shen ,  Daniel Pham ,  Sruthi Muralidharan

IPC: H01L21/308 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/845 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Abstract translation: 提供了用于提高集成电路（IC）设备的覆盖性能的方法。 具体地，IC器件（例如，鳍式场效应晶体管（FinFET））设置有形成在衬底上的氧化物层和衬垫层，其中氧化物层包括取向和覆盖标记，沉积在一组 通过衬垫层并进入衬底形成的开口，沉积在氧化物材料和衬垫层上的心轴层，以及在IC器件中图案化的一组鳍片，而不蚀刻对准和重叠标记。 利用这种方法，对准和重叠标记设置有翅片切割（FC）层，因此避免了精细化。