公开(公告)号：US09093560B2

公开(公告)日：2015-07-28

申请号：US14032740

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hung-Wei Liu ,  Rohit Pal ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Tae Hoon Lee ,  Songkram Srivathanakul ,  Danni Chen

IPC: H01L21/31 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract translation: 提供了通过控制由这些方法形成的介电材料和半导体器件的凹陷来促进栅极高度均匀性的方法。 所述方法包括例如用n型晶体管和p型晶体管形成半导体器件的晶体管，n型晶体管和p型晶体管包括多个牺牲栅极结构和在上表面处的保护掩模 的多个牺牲栅极结构; 在多个牺牲栅极结构之上和之间提供电介质材料; 部分致密化介电材料以形成部分致密化的电介质材料; 进一步致密化部分致密化的介电材料以产生改性的介电材料; 以及在改性介电材料上形成基本平坦的表面，以控制电介质材料凹陷和栅极高度。

公开(公告)号：US08927356B1

公开(公告)日：2015-01-06

申请号：US13919645

申请日：2013-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Puneet Khanna

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3065

CPC classification number: H01L21/823828 ,  H01L21/28017 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823814

Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.

Abstract translation: 公开了用于打开用于替换栅极工艺的多晶硅NFET和PFET栅极的方法。 实施例包括提供具有氮化物盖的多晶硅栅极; 限定多晶硅栅极的PFET和NFET区域，在氮化物盖上形成氮化物凸块; 用PMD将氮化物盖覆盖到氮化物凸块的顶部; 对PMD和氮化物凸块进行1：1干蚀刻; 以及对氮化物帽进行选择性的第二干蚀刻，直到多晶硅栅极的顶表面。 其他实施例包括在氮化物盖上形成氮化物凸块之后，使PMD凹陷以暴露氮化物盖; 用氮化物填料覆盖氮化物盖和氮化物凸块，形成平面氮化物表面; 并且将氮化物填充物，氮化物凸块和氮化物帽向下移动到多晶硅栅极。

公开(公告)号：US09349814B2

公开(公告)日：2016-05-24

申请号：US14730887

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hung-Wei Liu ,  Rohit Pal ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Tae Hoon Lee ,  Songkram Srivathanakul ,  Danni Chen

IPC: H01L29/76 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

公开(公告)号：US20140370697A1

公开(公告)日：2014-12-18

申请号：US13919645

申请日：2013-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Puneet Khanna

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/28

CPC classification number: H01L21/823828 ,  H01L21/28017 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823814

Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.

Abstract translation: 公开了用于打开用于替换栅极工艺的多晶硅NFET和PFET栅极的方法。 实施例包括提供具有氮化物盖的多晶硅栅极; 限定多晶硅栅极的PFET和NFET区域，在氮化物盖上形成氮化物凸块; 用PMD将氮化物盖覆盖到氮化物凸块的顶部; 对PMD和氮化物凸块进行1：1干蚀刻; 以及对氮化物帽进行选择性的第二干蚀刻，直到多晶硅栅极的顶表面。 其他实施例包括在氮化物盖上形成氮化物凸块之后，使PMD凹陷以暴露氮化物盖; 用氮化物填料覆盖氮化物盖和氮化物凸块，形成平面氮化物表面; 并且将氮化物填充物，氮化物凸块和氮化物帽向下移动到多晶硅栅极。

公开(公告)号：US20140227858A1

公开(公告)日：2014-08-14

申请号：US13765723

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US09257516B2

公开(公告)日：2016-02-09

申请号：US14505582

申请日：2014-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hsin-Neng Tai ,  Huey-Ming Wang

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/42364 ,  H01L29/66545

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract translation: 制造中的中间半导体结构包括基板。 多个栅极结构设置在衬底上，其中至少两个栅极结构由相邻栅极结构之间的牺牲材料隔开。 去除牺牲材料的一部分以在牺牲材料内形成开口，其中填充有具有高纵横比氧化物的填充材料。 去除多余的填充材料。 去除栅极结构的一部分以在栅极结构内形成栅极开口。 栅极开口填充有栅极盖材料，并且去除多余的栅极盖材料以形成覆盖栅极结构和牺牲材料的基本平坦的表面，以控制牺牲氧化物凹陷和栅极高度。

公开(公告)号：US20150333121A1

公开(公告)日：2015-11-19

申请号：US14810167

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US09385192B2

公开(公告)日：2016-07-05

申请号：US14810167

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

公开(公告)号：US09123771B2

公开(公告)日：2015-09-01

申请号：US13765723

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US08877580B1

公开(公告)日：2014-11-04

申请号：US13896807

申请日：2013-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hsin-Neng Tai ,  Huey-Ming Wang

IPC: H01L21/8238 ,  H01L29/423 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/42364 ,  H01L29/66545

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract translation: 制造中的中间半导体结构包括基板。 多个栅极结构设置在衬底上，其中至少两个栅极结构由相邻栅极结构之间的牺牲材料隔开。 去除牺牲材料的一部分以在牺牲材料内形成开口，其中填充有具有高纵横比氧化物的填充材料。 去除多余的填充材料。 去除栅极结构的一部分以在栅极结构内形成栅极开口。 栅极开口填充有栅极盖材料，并且去除多余的栅极盖材料以形成覆盖栅极结构和牺牲材料的基本平坦的表面，以控制牺牲氧化物凹陷和栅极高度。