公开(公告)号：US20150333121A1

公开(公告)日：2015-11-19

申请号：US14810167

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US20150270175A1

公开(公告)日：2015-09-24

申请号：US14219059

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Andy Chih-Hung Wei ,  Dae-han Choi ,  Mariappan Hariharaputhiran ,  Weihua Tong ,  Dae Geun Yang ,  Akshey Sehgal ,  Jing Wan

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/306 ,  H01L21/324 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/268 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/66795

Abstract: Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements.

Abstract translation: 本文提供了使用部分结晶的翅片硬掩模形成鳍状场效应晶体管（FinFET）器件的方法。 具体地说，将硬掩模图案化在衬底上，并且FinFET器件被退火以形成与一组非结晶硬掩模元件相邻的一组结晶的硬掩模元件。 在图案化的硬掩模的第一部分上提供掩模结构，以防止在退火期间该组非结晶硬掩模元件结晶。 在随后的翅片切割过程中，除去未结晶的掩模元件，同时保留结晶的掩模元件。 然后根据结晶化掩模元件的位置在FinFET器件中形成一组翅片。

公开(公告)号：US20140227858A1

公开(公告)日：2014-08-14

申请号：US13765723

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US09418899B1

公开(公告)日：2016-08-16

申请号：US14611769

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping Shen ,  Min-hwa Chi ,  Xusheng Wu ,  Weihua Tong ,  Haiting Wang

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/3215 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28568 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract translation: 提供一种形成用于nFET和pFET的RMG多WF层的方法，以及所得到的器件。 实施例包括形成Si翅片; 形成nFET RMG沟槽和pFET RMG沟槽; 在nFET和pFET RMG沟槽中形成第一Ti层; 在pFET RMG沟槽中以0°注入角垂直注入第一Ti层中的N 2; 对N 2注入的第一Ti层退火以在pFET RMG沟槽中形成TiN层; 剥离第一Ti层的未反应的Ti; 在nFET和pFET RMG沟槽中形成第二Ti层; 在0°垂直放置第二Ti层中的Al或C; 退火Al或C注入的第二Ti层，分别在nFET和pFET RMG沟槽的底部形成TiAl或TiC; 并用Al或W填充nFET和pFET RMG沟槽。

公开(公告)号：US09287180B2

公开(公告)日：2016-03-15

申请号：US14749245

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。

公开(公告)号：US09093476B2

公开(公告)日：2015-07-28

申请号：US13954289

申请日：2013-07-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括：具有第一侧，第二侧，暴露的第一端面和暴露的第二端面的翅片结构的沟道区。 形成在沟道区域的第一侧和第二侧上方的栅极。 该方法包括通过暴露的第一端表面和暴露的第二端表面将离子注入沟道区域。 此外，所述方法包括在所述通道区域的暴露的第一端面和暴露的第二端面附近形成所述鳍结构的源极/漏极区域。

公开(公告)号：US09385192B2

公开(公告)日：2016-07-05

申请号：US14810167

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

公开(公告)号：US20150294915A1

公开(公告)日：2015-10-15

申请号：US14749245

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。

公开(公告)号：US09123771B2

公开(公告)日：2015-09-01

申请号：US13765723

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。