公开(公告)号：US20150076622A1

公开(公告)日：2015-03-19

申请号：US14030506

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat Krishnan ,  Jinping Liu ,  Zhao Lun ,  Hui Zhan ,  Bongki Lee

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/2253 ,  H01L21/2652 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.

Abstract translation: 半导体结构包括设置在有源区上的半导体衬底，有源区和伪栅极结构。 在伪栅极结构和有源区域上设置包括底部氧化物层和顶部氮化物层的牺牲保形层，以在源极和漏极注入期间保护虚拟栅极。 使用诸如n型掺杂剂或p型掺杂剂的掺杂剂注入有源区域，以在有源区域中产生源极区域和漏极区域，之后去除牺牲保形层。

公开(公告)号：US10700173B2

公开(公告)日：2020-06-30

申请号：US15949730

申请日：2018-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Hong Yu ,  Yanping Shen ,  Wei Hong ,  Xing Zhang ,  Ruilong Xie ,  Haiting Wang ,  Hui Zhan ,  Yong Jun Shi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/165

Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.

公开(公告)号：US20190035633A1

公开(公告)日：2019-01-31

申请号：US15665183

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ashish Kumar Jha ,  Hui Zhan ,  Hong Yu ,  Zhenyu Hu ,  Haiting Wang ,  Edward Reis ,  Charles Vanleuvan

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/475

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material. An isotropic Fin reveal process is performed and the STI structure assists in equalizing fin heights and increasing active S/D region area/volume.

公开(公告)号：US10090382B1

公开(公告)日：2018-10-02

申请号：US15811957

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Xinyuan Dou ,  Hui Zhan ,  Zhenyu Hu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L27/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/027

Abstract: The disclosure relates to forming single diffusion break (SDB) and end isolation regions in an integrated circuit (IC) structure, and resulting structures. An IC structure according to the disclosure includes: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of gate structures; at least one single diffusion break (SDB) region positioned within the insulator region and one of the plurality of fins, the at least one SDB extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of gate structures.