公开(公告)号：US09443771B1

公开(公告)日：2016-09-13

申请号：US14935676

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Min-hwa Chi ,  Ashish Kumar Jha ,  Haiting Wang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823828 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/32155 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method of removing RMG sidewall layers, and the resulting device are provided. Embodiments include forming a TiN layer in nFET and pFET RMG trenches; forming an a-Si layer over the TiN layer; implanting O2 vertically in the a-Si layer; removing the a-Si layer and TiN layer from the side surfaces of the RMG trenches followed by the a-Si layer from the bottom surfaces; forming a TiN layer in the RMG trenches; forming a a-Si layer over the TiN layer; implanting O2 vertically in the a-Si layer; removing the a-Si layer and TiN layer from the side surfaces of the RMG trenches, the a-Si layer from the bottom surfaces, and a remainder of the TiN layer from only the nFET RMG trench; forming a Ti layer in the RMG trenches; implanting Al or C in the Ti layer vertically and annealing; and filling the RMG trenches with Al or W.

Abstract translation: 提供去除RMG侧壁层的方法，并且提供所得到的装置。 实施例包括在nFET和pFET RMG沟槽中形成TiN层; 在TiN层上形成a-Si层; 在a-Si层中垂直注入O2; 从RMG沟槽的侧表面除去a-Si层和TiN层，然后从底表面除去a-Si层; 在RMG沟槽中形成TiN层; 在TiN层上形成a-Si层; 在a-Si层中垂直注入O2; 从RMG沟槽的侧表面，从底表面的a-Si层和仅仅nFET RMG沟槽的TiN层的剩余部分去除a-Si层和TiN层; 在RMG沟槽中形成Ti层; 在Ti层中垂直注入Al或C并进行退火; 并用Al或W填充RMG沟槽。

公开(公告)号：US10192746B1

公开(公告)日：2019-01-29

申请号：US15665183

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ashish Kumar Jha ,  Hui Zhan ,  Hong Yu ,  Zhenyu Hu ,  Haiting Wang ,  Edward Reis ,  Charles Vanleuvan

IPC: H01L21/76 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/475

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material. An isotropic Fin reveal process is performed and the STI structure assists in equalizing fin heights and increasing active S/D region area/volume.

公开(公告)号：US10522679B2

公开(公告)日：2019-12-31

申请号：US15797380

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar Jha ,  Hong Yu ,  Xinyuan Dou ,  Xusheng Wu ,  Dongil Choi ,  Edmund K. Banghart ,  Md Khaled Hassan

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

公开(公告)号：US10396206B2

公开(公告)日：2019-08-27

申请号：US15643940

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar Jha ,  Haiting Wang ,  Wei Hong ,  Wei Zhao ,  Tae Jeong Lee ,  Zhenyu Hu

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/475 ,  H01L29/43 ,  H01L27/02 ,  H01L27/118

Abstract: A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.

公开(公告)号：US20190035633A1

公开(公告)日：2019-01-31

申请号：US15665183

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ashish Kumar Jha ,  Hui Zhan ,  Hong Yu ,  Zhenyu Hu ,  Haiting Wang ,  Edward Reis ,  Charles Vanleuvan

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/475

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material. An isotropic Fin reveal process is performed and the STI structure assists in equalizing fin heights and increasing active S/D region area/volume.

公开(公告)号：US09331159B1

公开(公告)日：2016-05-03

申请号：US14615470

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish Kumar Jha ,  Yan Ping Shen ,  Wei Hua Tong ,  Haiting Wang ,  Min-Hwa Chi

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/04 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L21/02233 ,  H01L21/30608 ,  H01L21/3083 ,  H01L21/31111 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/78

Abstract: Methods of fabricating transistors having raised active region(s) with at least partially angled upper surfaces are provided. The method includes, for instance: providing a gate structure disposed over a substrate, the gate structure including a conformal spacer layer; forming a raised active region adjoining a sidewall of the conformal spacer layer; providing a protective material over the raised active region; selectively etching-back the sidewall of the conformal spacer layer, exposing a side portion of the raised active region below the protective material; and etching the exposed side portion of the raised active region to partially undercut the protective material, wherein the etching facilitates defining, at least in part, an at least partially angled upper surface of the raised active region of the transistor.

Abstract translation: 提供了制造具有至少部分成角度的上表面的具有凸起的有源区域的晶体管的方法。 该方法包括例如：提供设置在衬底上的栅极结构，所述栅极结构包括共形间隔层; 形成邻接所述共形间隔层的侧壁的凸起的有源区; 在凸起的活动区域上提供保护材料; 选择性地蚀刻保形间隔层的侧壁，将凸起的有源区域的侧部暴露在保护材料下方; 并且蚀刻凸起的有源区域的暴露的侧部分以部分地切割保护材料，其中蚀刻有助于至少部分地限定晶体管的凸起的有源区的至少部分成角度的上表面。

公开(公告)号：US10008385B1

公开(公告)日：2018-06-26

申请号：US15612335

申请日：2017-06-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish Kumar Jha ,  Haiting Wang ,  Chih-Chiang Chang ,  Mitchell Rutkowski

IPC: H01L21/28 ,  H01L21/768

CPC classification number: H01L21/28132 ,  H01L21/76834 ,  H01L21/76897

Abstract: Methods of forming a sacrificial gate cap and a self-aligned contact for a device structure. A gate electrode is arranged between a first sidewall spacer and a second sidewall spacer. A top surface of the gate electrode is recessed to open a space above the top surface of the recessed gate electrode that partially exposes the first and second sidewall spacers. Respective sections of the first and second sidewall spacers, which are arranged above the top surface of the recessed gate electrode, are removed in order to increase a width of the space. A sacrificial cap is formed in the widened space.

公开(公告)号：US09147572B2

公开(公告)日：2015-09-29

申请号：US13896022

申请日：2013-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish Kumar Jha ,  Haiting Wang ,  Meng Luo ,  Yong Meng Lee

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/02071 ,  H01L21/28238 ,  H01L21/31144 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.

Abstract translation: 公开了将替代金属栅极的长度控制到设计的栅极栅极长度的方法以及所得到的器件。 实施例可以包括从形成空腔的衬底上方去除虚拟栅极，其中腔的侧表面衬有氧化间隔层，并且空腔的底表面衬有栅极氧化物层，保形地形成牺牲氧化物层 衬底和空腔，并且从空腔的底表面和衬底去除牺牲氧化物层，留下衬在腔的侧表面的牺牲氧化物间隔物。