公开(公告)号：US20150364426A1

公开(公告)日：2015-12-17

申请号：US14303714

申请日：2014-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti ,  Anurag Mittal ,  Manfred Eller

IPC: H01L23/538 ,  H01L23/66 ,  H01L29/06 ,  H01L27/06 ,  H01L29/94 ,  H01L27/08

CPC classification number: H01L27/0629 ,  H01L27/0805 ,  H01L29/94

Abstract: Embodiments of the present invention provide an improved decoupling capacitor structure. A contact region is disposed over a source/drain region of the decoupling capacitor structure. Each contact region is formed as a plurality of segments, wherein an inter-segment gap separates a segment of the plurality of segments from an adjacent segment of the plurality of segments. Embodiments may include multiple contact regions between two gate regions. Arrays of decoupling capacitors may arranged as an alternating “checkerboard” pattern of P-well and N-well structures, and may be oriented at a diagonal angle to a metallization layer to facilitate connections of multiple decoupling capacitors within the array.

Abstract translation: 本发明的实施例提供了一种改进的去耦电容器结构。 接触区域设置在去耦电容器结构的源极/漏极区域上。 每个接触区域形成为多个段，其中段间间隙将多个段中的段与多个段的相邻段分离。 实施例可以包括两个栅极区域之间的多个接触区域。 去耦电容器的阵列可以被布置为P阱和N阱结构的交替“棋盘”图案，并且可以以与金属化层对角的角度定向，以便于阵列内的多个去耦电容器的连接。

公开(公告)号：US20150001640A1

公开(公告)日：2015-01-01

申请号：US13927932

申请日：2013-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Johannes M. van Meer

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/7833

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

公开(公告)号：US20200035785A1

公开(公告)日：2020-01-30

申请号：US16045267

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti ,  Jae Gon Lee ,  Josef Watts

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/265

Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

公开(公告)号：US10475890B2

公开(公告)日：2019-11-12

申请号：US15728070

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hui Zang ,  Hong Yu ,  Zhenyu Hu ,  Scott Beasor ,  Erik Geiss ,  Jerome Ciavatti ,  Jae Gon Lee

IPC: H01L29/417 ,  H01L27/11 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.

公开(公告)号：US10121878B1

公开(公告)日：2018-11-06

申请号：US15711415

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/441 ,  H01L29/06 ,  H01L21/266

Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed on a substrate. A first well of a first conductivity type is arranged partially in the substrate and partially in the first fin. A second well of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. First and second source/drain regions of the second conductivity type are respectively formed within the first well in the first fin and within the second well in the second fin. Spaced-apart gate structures are formed that overlap with respective portions of the first fin. A doped region of the first conductivity type is arranged within the second well in the first fin between the first and second gate structures.

公开(公告)号：US10068902B1

公开(公告)日：2018-09-04

申请号：US15715220

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Yongjun Shi ,  Randy W. Mann ,  Yi Qi ,  Guowei Xu ,  Wei Hong ,  Jerome Ciavatti ,  Jae Gon Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66

Abstract: Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the method, sacrificial gates are removed from partially completed transistors, creating gate openings that expose sections of semiconductor fins between source/drain regions. Prior to forming replacement metal gates in the gate openings, additional process steps are performed so that, in the resulting IC structure, some transistors have different channel region heights and, thereby different effective channel widths, than others. These steps can include forming isolation regions in the bottoms of some gate openings. Additionally or alternatively, these steps can include filling some gate openings with a sacrificial material, recessing the sacrificial material to expose fin tops within those gate openings, either recessing the fin tops or forming isolation regions in the fin tops, and removing the sacrificial material. Also disclosed is an IC structure formed according to the method.

公开(公告)号：US09536991B1

公开(公告)日：2017-01-03

申请号：US15067435

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Min-hwa Chi

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/6681 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653

Abstract: A method of forming a single diffusion break includes patterning a fin hardmask disposed over a substrate. First and second fin arrays separated by an isolation region are etched into the substrate from the patterned fin hardmask. Any remaining fin hardmask being self-aligned with the fins. A first dielectric fill material is disposed and planarized over the arrays to expose top surfaces of the remaining fin hardmask. A second dielectric strip is formed over the first dielectric fill material to cover the isolation region and end portions of the remaining fin hardmask. Any exposed portions of the remaining fin hardmask are anisotropically etched away. The end portions of the remaining fin hardmask form base extensions of a base for a single diffusion break (SDB) in the isolation region. The first dielectric fill material and second dielectric strip are etched to complete formation of the base for the single diffusion break.

Abstract translation: 形成单个扩散断裂的方法包括图案化设置在基板上的散热片硬掩模。 由分离区隔开的第一和第二鳍状阵列从图案化的翅片硬掩模中蚀刻到基底中。 任何剩余的散热片硬掩模与翅片自对准。 第一介电填充材料在阵列上布置和平坦化以暴露剩余的散热片硬掩模的顶表面。 在第一介电填充材料上形成第二介质条以覆盖剩余的散热片硬掩模的隔离区域和端部。 剩余散热片硬掩模的任何暴露部分被各向异性地蚀刻掉。 剩余散热片硬掩模的端部形成用于隔离区域中的单个扩散断裂（SDB）的基部的基部延伸部。 蚀刻第一介电填充材料和第二介电条以完成单扩散断裂的基底的形成。

公开(公告)号：US09324827B1

公开(公告)日：2016-04-26

申请号：US14525744

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti

IPC: H01L29/66 ,  H01L29/872 ,  H01L29/06

CPC classification number: H01L29/66143 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/872

Abstract: A non-planar Schottky diode includes a semiconductor substrate of a first type, the first type including one of n-type and p-type. The structure further includes raised semiconductor structure(s) of a second type opposite the first type coupled to the substrate, isolation material surrounding a lower portion of the raised structure(s), a first well of the second type directly under the raised structure(s), a guard ring of the first type around an edge of a top portion of the first well, a conformal layer of silicide over a top portion of the raised structure(s) above the isolation material, and a common contact above the conformal layer of silicide. The non-planar Schottky diode can be fabricated with non-planar transistors, e.g., FinFETs.

Abstract translation: 非平面肖特基二极管包括第一类型的半导体衬底，第一类型包括n型和p型之一。 该结构还包括与耦合到衬底的第一类型相反的第二类型的凸起半导体结构，围绕凸起结构的下部的隔离材料，直立在凸起结构下方的第二类型的第一阱（ s），围绕第一阱的顶部的边缘的第一类型的保护环，在隔离材料上方的凸起结构的顶部上的硅化物的保形层，以及在保形层之上的公共接触 硅化物层。 非平面肖特基二极管可以用非平面晶体管制造，例如FinFET。

公开(公告)号：US09064868B2

公开(公告)日：2015-06-23

申请号：US13650233

申请日：2012-10-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Vara Vakada ,  Jerome Ciavatti

IPC: H01L29/66 ,  H01L23/522

CPC classification number: H01L23/5225 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate.

Abstract translation: 本文公开的一种说明性器件包括晶体管，其包括形成在半导体衬底中的栅电极和漏区，形成在衬底中的隔离结构，其中隔离结构横向地位于栅电极和漏区之间，法拉第屏蔽 其位于栅极电极和漏极区域之间并且隔离结构之上，其中法拉第屏蔽具有相对于衬底的上表面基本垂直取向的长轴。

公开(公告)号：US20150108580A1

公开(公告)日：2015-04-23

申请号：US14580834

申请日：2014-12-23

Applicant: Globalfoundries Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L27/06 ,  H01L29/08 ,  H01L29/735 ,  H01L29/78

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

Abstract translation: 本文公开的一种方法包括执行至少一个公共处理操作，以形成用于多个场效应晶体管中的每一个的多个第一栅极结构和在将形成双极晶体管的区域上方的多个第二栅极结构，并且执行离子 注入工艺和加热工艺以形成在所有第二栅极结构下延伸的连续掺杂发射极区域。 本文公开的器件包括具有第一栅极结构的第一多个场效应晶体管，具有位于发射极区域上方的发射极区域和多个第二栅极结构的双极晶体管，其中所述双极晶体管包括延伸的连续掺杂发射极区域 在所有多个第二栅极结构的全部下方。