公开(公告)号：US10325819B1

公开(公告)日：2019-06-18

申请号：US15920303

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3105

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

公开(公告)号：US10256089B2

公开(公告)日：2019-04-09

申请号：US15626732

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Haigou Huang ,  Jinsheng Gao ,  Tai Fong Chao

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28

Abstract: Interconnect structures and methods of forming an interconnect structure. A sacrificial contact is arranged between a first gate structure and a second gate structure. The sacrificial contact extends vertically to a source/drain region. A section of the sacrificial contact is removed to form a cut opening extending vertically to the source/drain region. A first dielectric layer is deposited in the cut opening, and is then partially removed to open a space in the cut opening that is arranged vertically above the first dielectric layer. A second dielectric layer is deposited that fills the space in the cut opening and forms a cap on the first dielectric layer. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US20180366324A1

公开(公告)日：2018-12-20

申请号：US15626732

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Haigou Huang ,  Jinsheng Gao ,  Tai Fong Chao

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L21/02378 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/28255 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/76888 ,  H01L29/41775

Abstract: Interconnect structures and methods of forming an interconnect structure. A sacrificial contact is arranged between a first gate structure and a second gate structure. The sacrificial contact extends vertically to a source/drain region. A section of the sacrificial contact is removed to form a cut opening extending vertically to the source/drain region. A first dielectric layer is deposited in the cut opening, and is then partially removed to open a space in the cut opening that is arranged vertically above the first dielectric layer. A second dielectric layer is deposited that fills the space in the cut opening and forms a cap on the first dielectric layer. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US09991363B1

公开(公告)日：2018-06-05

申请号：US15657594

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinsheng Gao ,  Haifeng Sheng ,  Jinping Liu ,  Huy Cao ,  Hui Zang

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32105 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437

Abstract: A contact etch stop layer includes a nitride layer formed over a sacrificial gate structure and a polysilicon layer formed over the nitride layer. During subsequent processing, the polysilicon layer is adapted to oxidize and form an oxide layer. The oxidation of the polysilicon layer effectively shields the underlying nitride contact etch stop layer from oxidation, which protects the mechanical integrity of the nitride layer.

公开(公告)号：US09935012B1

公开(公告)日：2018-04-03

申请号：US15361824

申请日：2016-11-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Haigou Huang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/027 ,  H01L21/308 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823412 ,  H01L29/16 ,  H01L29/66795

Abstract: Disclosed are methods of forming different shapes in different regions of a specific layer. In the methods, a first mask layer and an etch process are used to form first shapes in a first region. Subsequently, a second mask layer and additional etch process(es) are used to form second shapes in a second region. However, before the second shapes are formed, a sacrificial layer of a degradable material is deposited onto the first mask layer and within openings in the specific layer surrounding the first shapes, thereby protecting the first shapes during formation of the second shapes. After the second shapes are formed, the material of the sacrificial layer is degraded (e.g., oxidized, volatilized, burned-off, etc.) so as to selectively remove that material from surfaces of the first mask layer and the specific layer without impacting the profiles of either the first shapes or the second shapes.

公开(公告)号：US20190326416A1

公开(公告)日：2019-10-24

申请号：US15956306

申请日：2018-04-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Jiehui Shu ,  Chih-Chiang Chang ,  Xingzhao Shi ,  Jinsheng Gao ,  Huy Cao

IPC: H01L29/66 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate electrode is arranged in a lower portion of a trench in an interlayer dielectric layer, and a liner is formed inside an upper portion of the trench and over a top surface of the interlayer dielectric layer. A dielectric material is deposited in in the upper portion of the trench and over the liner on the top surface of the interlayer dielectric layer. The dielectric material is polished with a polishing process to remove the dielectric material from the liner on the top surface of the interlayer dielectric layer and to form a cap comprised of the dielectric material in the upper portion of the trench. The liner on the interlayer dielectric layer operates as a polish stop during the polishing process.

公开(公告)号：US10418455B2

公开(公告)日：2019-09-17

申请号：US15716287

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/321 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/092

Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

公开(公告)号：US10388562B2

公开(公告)日：2019-08-20

申请号：US15678229

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Daniel Jaeger ,  Xusheng Wu ,  Jinsheng Gao

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02

Abstract: A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

公开(公告)号：US10269654B1

公开(公告)日：2019-04-23

申请号：US15890246

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A replacement metal gate (RMG) process is performed in the gate region. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

公开(公告)号：US10204797B1

公开(公告)日：2019-02-12

申请号：US15890210

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Jessica Dechene ,  Haigou Huang

IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/02 ,  C23C16/36 ,  H01L21/67 ,  C23C16/56 ,  C23C16/26

Abstract: The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.