公开(公告)号：US20150279742A1

公开(公告)日：2015-10-01

申请号：US14242046

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L21/8234 ,  H01L21/321 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One method disclosed includes, among other things, forming a gate registration structure above an isolation region, wherein the gate registration structure comprises a plurality of layers of material, the uppermost layer of which is a polish-stop layer, forming first and second sacrificial gate structures above first and second active regions, respectively, wherein the first and second sacrificial gate structures abut and engage opposite sides of the gate registration structure, and performing at least one first chemical mechanical polishing (CMP) process to remove the gate cap layer so as to thereby expose a sacrificial gate electrode in each of the first and second sacrificial gate structures, wherein the uppermost layer of the gate registration structure serves as a polish-stop layer during the at least one first CMP process.

Abstract translation: 公开的一种方法包括在隔离区域之上形成栅极配准结构，其中栅极配准结构包括多层材料，其最上层是抛光停止层，形成第一和第二牺牲栅极 分别在第一和第二有源区域之上的结构，其中第一和第二牺牲栅极结构邻接并接合栅极对准结构的相对侧，并且执行至少一个第一化学机械抛光（CMP）工艺以移除栅极盖层，以便 从而在第一和第二牺牲栅极结构中的每一个中露出牺牲栅电极，其中栅极配准结构的最上层在至少一个第一CMP工艺期间用作抛光停止层。

公开(公告)号：US09093302B2

公开(公告)日：2015-07-28

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。