公开(公告)号：US09417501B2

公开(公告)日：2016-08-16

申请号：US14529243

申请日：2014-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Raghavasimhan Sreenivasan

IPC: G02B6/42 ,  G02F1/17 ,  G02B6/10 ,  G02B26/02 ,  H01L31/18

CPC classification number: G02F1/17 ,  G02B6/10 ,  G02B26/02 ,  H01L31/18

Abstract: Embodiments of the present invention provide an electrically controlled optical fuse. The optical fuse is activated electronically instead of by the light source itself. An applied voltage causes the fuse temperature to rise, which induces a transformation of a phase changing material from transparent to opaque. A gettering layer absorbs excess atoms released during the transformation.

Abstract translation: 本发明的实施例提供一种电控光熔丝。 光学保险丝以电子方式激活而不是由光源本身激活。 施加的电压导致熔丝温度升高，这导致相变材料从透明变为不透明。 吸收层吸收在转化期间释放的多余原子。

公开(公告)号：US20160172467A1

公开(公告)日：2016-06-16

申请号：US15062465

申请日：2016-03-07

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/2018 ,  H01L21/28238 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

公开(公告)号：US09257536B2

公开(公告)日：2016-02-09

申请号：US13867247

申请日：2013-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L29/66

CPC classification number: H01L29/66795

Abstract: FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region.

Abstract translation: 公开了FinFET结构和形成方法。 翅片形成在块状基底上。 在散装衬底上形成结晶绝缘体层，翅片从外延氧化物层伸出。 在从结晶绝缘体层突出的翅片周围形成栅极。 通过将结晶绝缘体层上的翅片合并形成翅片合并区域，在源漏区域中形成外延生长的半导体区域。

公开(公告)号：US09214397B2

公开(公告)日：2015-12-15

申请号：US13788689

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kerber ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842

Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

Abstract translation: 一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离 存在于第二导电装置区域上的高k栅介质层。 连接栅极导体形成在高k栅介质层的第一部分和第二部分上。 连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。 然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。 用含氧气氛曝光改变暴露的半导体器件的阈值电压。

公开(公告)号：US20150357434A1

公开(公告)日：2015-12-10

申请号：US14827510

申请日：2015-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

公开(公告)号：US20150214331A1

公开(公告)日：2015-07-30

申请号：US14168112

申请日：2014-01-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/2018 ,  H01L21/28238 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Abstract translation: 制造半导体器件的方法包括在半导体衬底上形成至少一个半导体鳍片。 在布置在散热片上的蚀刻停止层上形成多个栅极形成层。 多个栅极形成层包括由电介质材料形成的虚拟栅极层。 图案化多个栅极形成层以在蚀刻停止层上形成多个虚拟栅极元件。 每个伪栅极元件由电介质材料形成。 蚀刻形成在虚拟栅极元件上的间隔层，以在虚拟栅极元件的每个侧壁上形成间隔物。 位于每个伪栅元件之间的蚀刻停止层的一部分被蚀刻以暴露半导体鳍片的一部分。 半导体材料从半导体鳍片的暴露部分外延生长以形成源极/漏极区域。