公开(公告)号：US20200027979A1

公开(公告)日：2020-01-23

申请号：US16038384

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08

Abstract: One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.

公开(公告)号：US10263122B1

公开(公告)日：2019-04-16

申请号：US15828386

申请日：2017-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Lars Liebmann

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/808 ,  H01L29/788 ,  H01L27/088 ,  H01L21/302 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/3065

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor including a gate contact patterned in a self-aligned process. In one embodiment, we disclose a semiconductor device, including a semiconductor substrate and a first vertical field effect transistor (vFET) including a bottom source/drain (S/D) region disposed on the semiconductor substrate; a fin disposed above the bottom S/D region; a top source/drain (S/D) region disposed above the fin and having a top surface; and a gate having a top surface higher than the top surface of the top S/D region. A gate contact may be formed over the gate.

公开(公告)号：US10230000B2

公开(公告)日：2019-03-12

申请号：US15671605

申请日：2017-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Tek Po Rinus Lee ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

公开(公告)号：US20180261595A1

公开(公告)日：2018-09-13

申请号：US15455313

申请日：2017-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Katsunori Onishi ,  Tek Po Rinus Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method includes forming a first plurality of gate structures. A second plurality of gate structures is formed. A first spacer is formed on each of the first and second pluralities of gate structures. A first cavity is defined between the first spacers of a first pair of the first plurality of gate structures. A second cavity is defined between the first spacers of a second pair of the second plurality of gate structures. A second spacer is selectively formed in the second cavity on the first spacer of each of the gate structures of the second pair without forming the second spacer in the first cavity. A first contact is formed contacting the first spacers in the first cavity. A second contact is formed contacting the second spacers in the second cavity.

公开(公告)号：US20180102409A1

公开(公告)日：2018-04-12

申请号：US15833285

申请日：2017-12-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit product includes a FinFET device, a device isolation region that is positioned around a perimeter of the FinFET device, and an isolation protection layer that is positioned above the device isolation region. The FinFET device includes at least one fin, a gate structure, and a sidewall spacer, the device isolation region includes a first insulating material, and the isolation protection layer includes a material that is different from the first insulating material. A first portion of the isolation protection layer is positioned under a portion of the gate structure and under a portion of the sidewall spacer, wherein a second portion of the isolation protection layer is not positioned under the gate structure and is not positioned under the sidewall spacer, the first portion of the isolation protection layer having a thickness that is greater than a thickness of the second portion.

公开(公告)号：US10886178B2

公开(公告)日：2021-01-05

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Annie Levesque ,  Qun Gao ,  Hui Zang ,  Rishikesh Krishnan ,  Bharat Krishnan ,  Curtis Durfee

IPC: H01L29/167 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L21/02 ,  H01L29/40 ,  H01L23/535

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US10242982B2

公开(公告)日：2019-03-26

申请号：US15455313

申请日：2017-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Katsunori Onishi ,  Tek Po Rinus Lee

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/423

Abstract: A method includes forming a first plurality of gate structures. A second plurality of gate structures is formed. A first spacer is formed on each of the first and second pluralities of gate structures. A first cavity is defined between the first spacers of a first pair of the first plurality of gate structures. A second cavity is defined between the first spacers of a second pair of the second plurality of gate structures. A second spacer is selectively formed in the second cavity on the first spacer of each of the gate structures of the second pair without forming the second spacer in the first cavity. A first contact is formed contacting the first spacers in the first cavity. A second contact is formed contacting the second spacers in the second cavity.

公开(公告)号：US09876077B1

公开(公告)日：2018-01-23

申请号：US15197944

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region.

公开(公告)号：US09570552B1

公开(公告)日：2017-02-14

申请号：US15076842

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Jinping Liu

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/7843 ,  H01L29/785

Abstract: A method of forming symmetrical stress liners to maintain strain in CMOS vertical NW FETs and the resulting device are provided. Embodiments include providing a doped semiconductor layer on an upper surface of a substrate; providing a semiconductor nanowire on the doped semiconductor layer; forming a first stress layer on the doped semiconductor layer surrounding the semiconductor nanowire; forming a gate electrode layer on a portion of the first stress layer on opposite sides of the semiconductor nanowire; forming a gate dielectric layer on the first stress layer between the gate electrode layer and the semiconductor nanowire; forming an oxide layer on a remaining portion of the first stress layer; forming a second stress layer on the oxide layer, the gate dielectric layer and the gate electrode layer; and forming contacts to the gate electrode layer, the semiconductor nanowire, and the doped semiconductor layer.

Abstract translation: 提供形成对称应力衬垫以维持CMOS垂直NW FET中的应变以及所得到的器件的方法。 实施例包括在衬底的上表面上提供掺杂半导体层; 在所述掺杂半导体层上提供半导体纳米线; 在围绕半导体纳米线的掺杂半导体层上形成第一应力层; 在所述半导体纳米线的相对侧上的所述第一应力层的一部分上形成栅极电极层; 在栅极电极层和半导体纳米线之间的第一应力层上形成栅极电介质层; 在所述第一应力层的剩余部分上形成氧化物层; 在氧化物层，栅极电介质层和栅极电极层上形成第二应力层; 以及与栅电极层，半导体纳米线和掺杂半导体层形成接触。