公开(公告)号：US20160233333A1

公开(公告)日：2016-08-11

申请号：US15040981

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Kiok Boone Elgin QUEK

IPC: H01L29/78 ,  H01L27/22 ,  H01L43/12 ,  H01L29/06

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L29/0669 ,  H01L29/165 ,  H01L29/7834 ,  H01L29/7848

Abstract: Memory cells and methods of forming memory cells are disclosed. The memory cell includes a substrate and a select transistor. The select transistor includes a gate disposed over the substrate between first and second source/drain (S/D) terminals. The first and second S/D terminals are configured such that a resistance at the second S/D terminal is higher than a resistance at the first S/D terminal. A dielectric layer disposed over the substrate includes a plurality of inter level dielectric (ILD) layers. A lower portion of the dielectric layer includes a first contact level and a first metal level. A first contact plug disposed within the first contact level connects the first S/D terminal to a first metal line in the first metal level. A magnetic tunnel junction (MTJ) element is disposed directly on and in contact with a top of the first metal line.

Abstract translation: 公开了存储单元和形成存储单元的方法。 存储单元包括衬底和选择晶体管。 选择晶体管包括设置在第一和第二源极/漏极（S / D）端子之间的衬底上的栅极。 第一和第二S / D端子被配置为使得第二S / D端子处的电阻高于第一S / D端子处的电阻。 布置在衬底上的电介质层包括多个级间电介质层（ILD）层。 电介质层的下部包括第一接触电平和第一金属电平。 设置在第一接触电平内的第一接触插头将第一S / D端子连接到第一金属层中的第一金属线。 磁性隧道结（MTJ）元件直接设置在第一金属线的顶部并与之接触。

公开(公告)号：US20150188047A1

公开(公告)日：2015-07-02

申请号：US14633508

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng TAN ,  Eng Huat TOH ,  Elgin QUEK

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1675 ,  H01L45/1691

Abstract: An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode.

Abstract translation: 公开了一种具有垂直BJT选择器的RRAM。 实施例包括在衬底中限定STI区域，在衬底中注入掺杂剂以在STI区域的底部周围和下方形成第一极性，在STI区域的相对侧上的阱上的第二极性沟道，以及第一 在衬底的表面上的每个通道上的极性有源区域，在有源区域和STI区域上形成RRAM衬垫，在RRAM衬垫上形成牺牲顶部电极，在牺牲顶部电极的相对侧上形成间隔物，注入第二极性 在牺牲顶部电极的相对侧上的有源区域中形成掺杂剂，在间隔物附近形成氧化硅，去除形成空腔的牺牲顶部电极的至少一部分，在空腔中形成邻近间隔物的内部间隔物和顶部电极。

公开(公告)号：US20150129975A1

公开(公告)日：2015-05-14

申请号：US14078554

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping ZHENG ,  Eng Huat TOH ,  Elgin Kiok Boone QUEK

IPC: H01L27/115 ,  H01L49/02

CPC classification number: G11C17/14 ,  H01L27/11206 ,  H01L45/04 ,  H01L45/1206 ,  H01L45/146 ,  H01L45/165 ,  H01L45/1675

Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.

Abstract translation: 提出了用于形成装置的装置和方法。 该器件包括具有器件区域的衬底和围绕器件区域的第一和第二隔离区域。 该器件包括具有设置在器件区域上的单个晶体管的多时间可编程（MTP）存储单元。 该晶体管包括栅极，该栅极在栅极电介质上方具有包括可编程电阻层的栅电极。 栅极电介质设置在衬底中具有第一和第二子区域的沟道区域上。 布置在第一和第二子区域上方的栅极电介质具有不同的特性，使得当存储单元被编程时，在第一或第二子区域之一之上的可编程电阻层的一部分对于相对于 在另一个第一或第二子区域之上的可编程电阻。

公开(公告)号：US20150001608A1

公开(公告)日：2015-01-01

申请号：US14253878

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng TAN ,  Eng Huat TOH ,  Jeoung Mo KOO ,  Danny SHUM ,  Elgin Kiok Boone QUEK

IPC: H01L29/788

CPC classification number: H01L29/42324 ,  G11C16/0425 ,  H01L27/11558 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. A non-volatile MTP memory cell includes a substrate, first and second wells disposed in the substrate, a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over the second well and sharing a diffusion region. The memory cell further includes a control gate disposed over the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and the second wells.

Abstract translation: 提出了一种用于非易失性存储单元的简单且无成本的多时间可编程（MTP）结构的实施例。 非易失性MTP存储单元包括衬底，设置在衬底中的第一和第二阱，具有选择栅极的第一晶体管和具有彼此相邻并且布置在第二阱上并且共享扩散区域的浮置栅极的第二晶体管。 存储单元还包括设置在第一阱上的控制栅极。 控制栅极耦合到浮动栅极，并且控制和浮置栅极包括延伸穿过第一和第二阱的相同栅极层。

公开(公告)号：US20130307038A1

公开(公告)日：2013-11-21

申请号：US13947118

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Jae Gon LEE ,  Chung Foong TAN ,  Elgin QUEK

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849

Abstract: A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility.

Abstract translation: 翅片型晶体管包括在衬底表面上的用于将晶体管的栅极与衬底隔离的介质层。 电介质层包括非选择性蚀刻的表面，以产生翅片结构的顶部，其具有减小横跨晶片的高度变化。 鳍型晶体管还可以包括埋置的应力源和/或升高或嵌入的升高的S / D应力源，以引起通道中的应变以改善载流子迁移率。

公开(公告)号：US20230280378A1

公开(公告)日：2023-09-07

申请号：US17684683

申请日：2022-03-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Yongshun SUN

IPC: G01R15/20 ,  G01R33/07

CPC classification number: G01R15/202 ,  G01R33/077

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an on-chip current sensor. The on-chip current sensor includes: a vertical Hall sensor; and a current carrying conductor in a first wiring layer above the vertical Hall sensor.

公开(公告)号：US20230076182A1

公开(公告)日：2023-03-09

申请号：US17469227

申请日：2021-09-08

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping ZHENG ,  Eng Huat TOH

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  G01K7/36 ,  G01R33/09 ,  G11C11/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to temperature sensors with programmable magnetic tunnel junction structures and methods of manufacture. A structure includes a resistor material connected in series with a programmable magnetic tunnel junction structure in a Wheatstone bridge configuration.

公开(公告)号：US20210399055A1

公开(公告)日：2021-12-23

申请号：US16903503

申请日：2020-06-17

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Desmond Jia Jun LOY ,  Eng Huat TOH ,  Shyue Seng TAN

IPC: H01L27/24 ,  H01L45/00 ,  G11C11/56 ,  G11C13/00

Abstract: A memory device may be provided, including first, second and third electrodes, first and second mask elements and a switching layer. The first mask element may be arranged over a portion of and laterally offset from the first electrode. The second electrode may be arranged over the first mask element. The second mask element may be arranged over the second electrode. The third electrode may be arranged over a portion of and laterally offset from the second mask element. The switching layer may be arranged between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.

公开(公告)号：US20210066514A1

公开(公告)日：2021-03-04

申请号：US16556333

申请日：2019-08-30

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang WANG ,  Shyue Seng TAN ,  Eng Huat TOH

IPC: H01L31/02 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/0392 ,  H01L31/107 ,  H01L31/18

Abstract: A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer.

公开(公告)号：US20210020834A1

公开(公告)日：2021-01-21

申请号：US16513745

申请日：2019-07-17

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Desmond Jia Jun Loy ,  Eng Huat TOH ,  Shyue Seng TAN

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory device may include at least one inert electrode, at least one mask element arranged over the at least one inert electrode, a switching layer arranged over the at least one mask element and the at least one inert electrode, and at least one active electrode arranged over the switching layer. Both of the at least one mask element and the switching layer may be in contact with a top surface of the at least one inert electrode. The switching layer in this memory device may thus include corners at which the conductive filaments may be confined. This memory device may be formed with a process that may utilize the at least one mask element to help reduce the chances of shorting between the inert and active electrodes.