公开(公告)号：US11355409B2

公开(公告)日：2022-06-07

申请号：US16405325

申请日：2019-05-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/66 ,  H01L23/367 ,  H01L29/08 ,  H01L21/48 ,  H01L29/417 ,  H01L29/732

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

公开(公告)号：US11862717B2

公开(公告)日：2024-01-02

申请号：US17456395

申请日：2021-11-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Alvin J. Joseph ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/66 ,  H01L29/735 ,  H01L29/08 ,  H01L29/15 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/158 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.

公开(公告)号：US11605649B2

公开(公告)日：2023-03-14

申请号：US17306078

申请日：2021-05-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Alvin J. Joseph ,  Ramsey Hazbun

IPC: H01L27/12 ,  H01L21/762 ,  H01L23/66 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.

公开(公告)号：US11387353B2

公开(公告)日：2022-07-12

申请号：US16907600

申请日：2020-06-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Alvin J. Joseph ,  William J. Taylor, Jr. ,  Jeffrey B. Johnson

IPC: H01L29/68 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L27/112

Abstract: A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.

公开(公告)号：US11195715B2

公开(公告)日：2021-12-07

申请号：US16821228

申请日：2020-03-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Cameron Luce ,  Ramsey Hazbun ,  Mark Levy ,  Anthony K. Stamper ,  Alvin J. Joseph

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/324

Abstract: Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

公开(公告)号：US20210287902A1

公开(公告)日：2021-09-16

申请号：US16815070

申请日：2020-03-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

IPC: H01L21/02

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

公开(公告)号：US11764060B2

公开(公告)日：2023-09-19

申请号：US15584121

申请日：2017-05-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Alvin J. Joseph ,  Michael J. Zierak

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L21/02667 ,  H01L21/26506 ,  H01L21/76224 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02532 ,  H01L21/02595

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.

公开(公告)号：US20230057695A1

公开(公告)日：2023-02-23

申请号：US17509327

申请日：2021-10-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Alexander Derrickson ,  Judson R. Holt ,  John J. Pekarik

IPC: H01L29/08 ,  H01L29/735 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to lateral bipolar transistors and methods of manufacture. The structure includes: an extrinsic base comprising semiconductor material; an intrinsic base comprising semiconductor material which is located below the extrinsic base; a polysilicon emitter on a first side of the extrinsic base; a raised collector on a second side of the extrinsic base; and sidewall spacers on the extrinsic base which separate the extrinsic base from the polysilicon emitter and the raised collector.

公开(公告)号：US20220189821A1

公开(公告)日：2022-06-16

申请号：US17123184

申请日：2020-12-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Alvin J. Joseph

IPC: H01L21/762 ,  H01L21/763 ,  H01L23/367 ,  H01L27/12

Abstract: A structure includes an active device over an area of a substrate, and a heat spreading isolation structure adjacent the active device. The isolation structure includes a dielectric layer above a heat-conducting layer. The heat-conducting layer may include polycrystalline graphite. The heat-conducting layer provides a heat sink, which provides a high thermal conductivity path for heat with low electrical conductivity. The heat-conducting layer may extend into the substrate. The substrate may include an SOI substrate in which case the heat-conducting layer may extend through the buried insulator thereof.

公开(公告)号：US11264457B1

公开(公告)日：2022-03-01

申请号：US16953897

申请日：2020-11-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark Levy ,  Siva P. Adusumilli ,  Steven M. Shank ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L21/763 ,  H01L27/06 ,  H01L21/762

Abstract: Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.