EMBEDDED PACKAGING FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS
    11.
    发明申请
    EMBEDDED PACKAGING FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS 有权
    嵌入式封装用于包含侧向GaN功率晶体管的器件和系统

    公开(公告)号:US20160240471A1

    公开(公告)日:2016-08-18

    申请号:US15027012

    申请日:2015-04-15

    Abstract: Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.

    Abstract translation: 公开了包括横向GaN功率晶体管的器件和系统的嵌入式封装。 包装组件适用于大面积高功率GaN晶体管,并且包括GaN功率晶体管和包括三级互连结构的封装组件的组件。 在优选实施例中,三电平互连结构包括片上金属层,铜再分布层和封装金属层,其中存在通过三个级别分级/施加电流片上的刻度或锥形接触面积, 在GaN功率器件的有源区域上结合/收集芯片外的电流与分布式触点。 该嵌入式封装组件提供适合于用于高电压/高电流应用的大面积高功率GaN晶体管的器件和系统的低电感,低电阻互连结构。

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