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    EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES
    2.
    发明申请
    EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220020669A1

    公开(公告)日：2022-01-20

    申请号：US16928305

    申请日：2020-07-14

    Applicant: GaN Systems Inc.

    Inventor： Cameron MCKNIGHT-MACNEIL ,  Greg P. KLOWAK

    IPC: H01L23/495 ,  H01L23/482 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L29/20 ,  H01L29/778 ,  H01L23/00

    Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. Where a solder resist coating is provided, a dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, is provided between the solder resist coating and underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

    EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES
    3.
    发明申请
    EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220246503A1

    公开(公告)日：2022-08-04

    申请号：US17728220

    申请日：2022-04-25

    Applicant: GaN Systems Inc.

    Inventor： Cameron MCKNIGHT-MACNEIL ,  Greg P. KLOWAK

    IPC: H01L23/495 ,  H01L23/482 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778 ,  H01L23/00 ,  H01L23/31

    Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

    GaN SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FABRICATION BY SUBSTRATE REPLACEMENT
    5.
    发明申请
    GaN SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FABRICATION BY SUBSTRATE REPLACEMENT 有权
    GaN半导体器件结构和通过衬底替代制造的方法

    公开(公告)号：US20160380090A1

    公开(公告)日：2016-12-29

    申请号：US15078023

    申请日：2016-03-23

    Applicant: GaN Systems Inc.

    Inventor： John ROBERTS ,  Greg P. KLOWAK ,  Cameron MCKNIGHT-MACNEIL

    IPC: H01L29/778 ,  H01L29/205 ,  H01L21/66 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L23/34 ,  H01L29/20 ,  H01L27/095

    CPC classification number: H01L23/528 ,  H01L22/32 ,  H01L23/36 ,  H01L23/3737 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

    Abstract: Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.

    Abstract translation: 公开了包括高电流/高电压GaN半导体器件的器件和系统。 包括横向GaN晶体管的GaN管芯夹在上覆的集管和下面的复合热介电层之间。 制造包括提供在低成本硅衬底（GaN-on-Si裸片）上制造的常规GaN器件结构，将GaN-Si衬底管芯的源极，漏极和栅极接触焊盘机械地和电连接到导电轨道的相应接触区域 的头部，然后完全去除硅衬底。 外延层堆叠的暴露的基底表面涂覆有复合介电热层。 优选地，集管包括具有与GaN外延层堆叠匹配的CTE的陶瓷电介质支撑层。 热介电层包括高介电强度的热塑性聚合物和具有高导热性的介电填料。 与常规的GaN-on器件结构相比，该结构提供了改进的电击穿电阻和有效的散热。

    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES
    6.
    发明申请
    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES 有权
    用于大面积氮化物半导体器件的容错设计

    公开(公告)号：US20160284829A1

    公开(公告)日：2016-09-29

    申请号：US15032824

    申请日：2014-10-28

    Applicant: GAN SYSTEMS INC.

    Inventor： Greg P. KLOWAK ,  Cameron MCKNIGHT-MACNEIL ,  Howard TWEDDLE ,  Ahmad MIZAN ,  Nigel SPRINGETT

    IPC: H01L29/778 ,  H01L21/66 ,  H01L29/16 ,  H01L29/417 ,  H01L29/205 ,  H01L29/861 ,  H01L29/20 ,  H01L29/06

    CPC classification number: H01L29/7787 ,  H01L22/14 ,  H01L22/22 ,  H01L22/32 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighbouring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

    Abstract translation: 提供了大面积氮化物半导体器件的容错设计，便于测试和隔离缺陷区域。 晶体管包括多个岛的阵列，每个岛包括有源区，源极和漏极以及栅电极。 每个岛的电极在阵列的至少一个方向上与相邻岛的电极电隔离。 提供源极，漏极和栅极接触焊盘，以实现每个岛的电气测试。 在岛的电测试以识别有缺陷的岛之后，形成覆盖的电连接以使源电极并联连接，漏电极并联，并且互连栅电极以形成具有大栅极宽度Wg的公共栅电极。 选择性地向好的岛屿提供互连，同时电隔离有缺陷的岛屿。 这种方法使得制造大面积GaN器件（包括混合器件）在经济上是可行的。

    HIGH CURRENT LATERAL GaN TRANSISTORS WITH SCALABLE TOPOLOGY AND GATE DRIVE PHASE EQUALIZATION
    7.
    发明申请
    HIGH CURRENT LATERAL GaN TRANSISTORS WITH SCALABLE TOPOLOGY AND GATE DRIVE PHASE EQUALIZATION 审中-公开

    公开(公告)号：US20190081623A1

    公开(公告)日：2019-03-14

    申请号：US15704458

    申请日：2017-09-14

    Applicant: GaN Systems Inc.

    Inventor： Ahmad MIZAN ,  Greg P. KLOWAK ,  Xiaodong CUI

    IPC: H03K17/081 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522

    Abstract: Large area, high current, lateral GaN power transistors are implemented using an on-chip interconnect topology wherein the transistor is arranged as an array of sections, each section comprising a set of transistor islands; gate and source buses that form each gate drive loop have substantially the same track widths; the source bus runs over or under the gate bus, and the tracks are inductively coupled to provide flux cancellation in the gate drive loop, thereby reducing parasitic inductances. The gate delay in each gate drive loop is reduced, minimizing the gate drive phase difference across the transistor. An overlying current redistribution layer preferably has a track width no greater than that of the underlying source and drain buses, for efficient coupling. This topology provides improved scalability, enabling fabrication of multi-section, large scale, high current lateral GaN transistors with reduced gate drive loop inductance, for improved operational stability.

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